公开(公告)号：US20240312876A1

公开(公告)日：2024-09-19

申请号：US18671580

申请日：2024-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Youbo Lin

IPC: H01L23/482 ,  H01L21/764 ,  H01L21/768 ,  H01L23/498 ,  H01L29/417 ,  H01L29/49

CPC classification number: H01L23/4821 ,  H01L21/764 ,  H01L21/76832 ,  H01L23/49833 ,  H01L23/49894 ,  H01L29/41775 ,  H01L29/4991 ,  H01L2221/1042

Abstract: Interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the interconnects are disclosed herein. An exemplary interconnect is disposed in an insulating layer. The interconnect has a metal contact, a contact isolation layer surrounding sidewalls of the metal contact, and an air gap disposed between the contact isolation layer and the insulating layer. An air gap seal for the air gap has a first portion disposed over a top surface of the contact isolation layer, but not disposed on a top surface of the insulating layer, and a second portion disposed between the contact isolation layer and the insulating layer, such that the second portion surrounds a top portion of sidewalls of the metal contact. The air gap seal may include amorphous silicon and/or silicon oxide. The contact isolation layer may include silicon nitride. The insulating layer may include silicon oxide.

公开(公告)号：US11854896B2

公开(公告)日：2023-12-26

申请号：US17213420

申请日：2021-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Ying-Keung Leung ,  Huiling Shang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/823418 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/088 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/78696

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (S/D) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk S/D feature is separated from the substrate by a first air gap, and the bulk S/D feature is separated from the inner spacers by second air gaps.

公开(公告)号：US20230387199A1

公开(公告)日：2023-11-30

申请号：US18446665

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bwo-Ning Chen ,  Xusheng Wu ,  Pin-Ju Liang ,  Chang-Miao Liu ,  Shih-Hao Lin

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/66742 ,  H01L21/02603 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/78696

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.

公开(公告)号：US11444179B2

公开(公告)日：2022-09-13

申请号：US16953598

申请日：2020-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Chang-Miao Liu ,  Huiling Shang

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/08 ,  H01L29/423 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L21/265 ,  H01L21/225

Abstract: A semiconductor structure includes a semiconductor substrate, an oxide layer disposed over the semiconductor substrate, a high-k metal gate structure (HKMG) interleaved with the stack of semiconductor layers, and an epitaxial source/drain (S/D) feature disposed adjacent to the HKMG, wherein a bottom portion of the epitaxial S/D feature is defined by the oxide layer.

公开(公告)号：US20220262708A1

公开(公告)日：2022-08-18

申请号：US17739826

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Youbo Lin

IPC: H01L23/482 ,  H01L21/764 ,  H01L21/768 ,  H01L23/498 ,  H01L29/417 ,  H01L29/49

Abstract: Interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the interconnects are disclosed herein. An exemplary interconnect is disposed in an insulating layer. The interconnect has a metal contact, a contact isolation layer surrounding sidewalls of the metal contact, and an air gap disposed between the contact isolation layer and the insulating layer. An air gap seal for the air gap has a first portion disposed over a top surface of the contact isolation layer, but not disposed on a top surface of the insulating layer, and a second portion disposed between the contact isolation layer and the insulating layer, such that the second portion surrounds a top portion of sidewalls of the metal contact. The air gap seal may include amorphous silicon and/or silicon oxide. The contact isolation layer may include silicon nitride. The insulating layer may include silicon oxide.

公开(公告)号：US11387146B2

公开(公告)日：2022-07-12

申请号：US16931703

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Lun Min ,  Xusheng Wu ,  Chang-Miao Liu

IPC: H01L21/8234 ,  H01L21/764 ,  H01L27/088

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.

公开(公告)号：US11145650B2

公开(公告)日：2021-10-12

申请号：US16656609

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Chang-Miao Liu ,  Huiling Shang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/02

Abstract: Integrated circuit devices and methods of forming the same are provided. An integrated circuit device in an embodiment includes a first multi-gate active region over a substrate, a second multi-gate active region over the substrate, a first gate structure over the first multi-gate active region, a second gate structure over the second multi-gate active region, and a dielectric feature disposed between the first gate structure and the second gate structure. The dielectric feature includes an oxygen-free layer in contact with the first gate structure and the second gate structure, a silicon oxide layer over the oxygen-free layer, and a transition layer disposed between the oxygen-free layer and the silicon oxide layer. An oxygen content of the transition layer is smaller than an oxygen content of the silicon oxide layer.

公开(公告)号：US20210273078A1

公开(公告)日：2021-09-02

申请号：US16953598

申请日：2020-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Chang-Miao Liu ,  Huiling Shang

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/08 ,  H01L29/423 ,  H01L21/762

Abstract: A semiconductor structure includes a semiconductor substrate, an oxide layer disposed over the semiconductor substrate, a high-k metal gate structure (HKMG) interleaved with the stack of semiconductor layers, and an epitaxial source/drain (S/D) feature disposed adjacent to the HKMG, wherein a bottom portion of the epitaxial S/D feature is defined by the oxide layer.

公开(公告)号：US20210098603A1

公开(公告)日：2021-04-01

申请号：US16820175

申请日：2020-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bwo-Ning Chen ,  Xusheng Wu ,  Chang-Miao Liu ,  Shih-Hao Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L21/768

Abstract: A semiconductor structure includes source/drain (S/D) features disposed over a semiconductor substrate, a metal gate stack disposed between the S/D features, where the metal gate stack traverses a channel region between the S/D features, gate spacers disposed on sidewalls of the metal gate stack, and an etch-stop layer (ESL) disposed over the gate spacers and the S/D features. The semiconductor structure further includes an oxide liner disposed on the ESL, where the oxide liner includes silicon oxide and silicon dioxide, and an interlayer dielectric (ILD) layer disposed on the oxide liner, where composition of the ILD layer is different from composition of the oxide liner.

公开(公告)号：US20210066457A1

公开(公告)日：2021-03-04

申请号：US16735379

申请日：2020-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bwo-Ning Chen ,  Xusheng Wu ,  Chang-Miao Liu

IPC: H01L29/10 ,  H01L27/092 ,  H01L29/78 ,  H01L29/161 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/265 ,  H01L29/66

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The structure includes a semiconductor substrate; a fin extending above the semiconductor substrate, wherein the fin includes a first layer over the semiconductor substrate and a second layer over the first layer, wherein the first layer includes silicon germanium having a first concentration of germanium, and wherein the second layer includes silicon germanium having a second concentration of germanium less than the first concentration of germanium; and a gate stack disposed over the fin.