Invention Grant
- Patent Title: Apparatus with electronic circuitry having reduced leakage current and associated methods
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Application No.: US16836795Application Date: 2020-03-31
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Publication No.: US11646735B2Publication Date: 2023-05-09
- Inventor: Mohamed M. Elsayed
- Applicant: Silicon Laboratories Inc.
- Applicant Address: US TX Austin
- Assignee: Silicon Laboratories Inc.
- Current Assignee: Silicon Laboratories Inc.
- Current Assignee Address: US TX Austin
- Agency: Law Offices of Maximilian R. Peterson
- Main IPC: G01R31/26
- IPC: G01R31/26 ; G11C8/08 ; H01L21/70 ; H03K17/06 ; G11C8/00 ; H03K19/00 ; H03K19/003 ; H03K17/16 ; H03K19/0185
Abstract:
An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.
Public/Granted literature
- US20200266820A1 Apparatus with Electronic Circuitry Having Reduced Leakage Current and Associated Methods Public/Granted day:2020-08-20
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