公开(公告)号：US11646735B2

公开(公告)日：2023-05-09

申请号：US16836795

申请日：2020-03-31

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed M. Elsayed

IPC: G01R31/26 ,  G11C8/08 ,  H01L21/70 ,  H03K17/06 ,  G11C8/00 ,  H03K19/00 ,  H03K19/003 ,  H03K17/16 ,  H03K19/0185

CPC classification number: H03K19/0013 ,  H03K17/162 ,  H03K19/003 ,  H03K19/0185 ,  H03K2217/0036

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.

公开(公告)号：US20200266820A1

公开(公告)日：2020-08-20

申请号：US16836795

申请日：2020-03-31

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed M. Elsayed

IPC: H03K19/00 ,  H03K17/16 ,  H03K19/003

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.

公开(公告)号：US10659045B2

公开(公告)日：2020-05-19

申请号：US15634716

申请日：2017-06-27

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed M. Elsayed

IPC: G01R31/26 ,  G11C8/08 ,  H01L21/70 ,  H03K17/06 ,  G11C8/00 ,  H03K19/00 ,  H03K19/003 ,  H03K17/16 ,  H03K19/0185

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.

公开(公告)号：US20190051368A1

公开(公告)日：2019-02-14

申请号：US15676743

申请日：2017-08-14

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed M. Elsayed

IPC: G11C27/02 ,  H03K17/16

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to receive an input signal. The first switch is further coupled to a first capacitor. The S/H circuit further includes a buffer coupled to the first switch. In addition, the S/H circuit includes a voltage source coupled to an input of the buffer to apply an offset voltage to the input of the buffer.

公开(公告)号：US20190051367A1

公开(公告)日：2019-02-14

申请号：US15676731

申请日：2017-08-14

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed M. Elsayed

IPC: G11C27/02 ,  H03K17/16

CPC classification number: G11C27/024 ,  H03K17/161

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch to provide an input signal that is to be sampled, and a second switch coupled to receive the sampled signal. The second switch is further coupled to a capacitor. The S/H circuit further includes at least one native transistor coupled to the second switch and to the capacitor.

公开(公告)号：US20220148667A1

公开(公告)日：2022-05-12

申请号：US17587633

申请日：2022-01-28

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed M. Elsayed

IPC: G11C27/02 ,  H03K17/687

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches.

公开(公告)号：US10788376B2

公开(公告)日：2020-09-29

申请号：US15717924

申请日：2017-09-27

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed M. Elsayed ,  Kenneth W. Fernald

IPC: G01K7/02 ,  G05F1/56 ,  H03K5/24 ,  G05F3/30 ,  G01K7/01

Abstract: An apparatus includes a temperature measurement circuit. The temperature measurement circuit includes a bandgap circuit including an amplifier having an offset voltage that is compensated by using a set of trimming bits. The bandgap circuit provides first and second voltages related to a temperature to be measured. The temperature measurement circuit further includes a measuring circuit coupled to receive the first and second voltages. The measuring circuit further includes a comparator coupled to receive the first and second voltages, wherein the measuring circuit derives a temperature measurement from the first and second voltages.

公开(公告)号：US20180375507A1

公开(公告)日：2018-12-27

申请号：US15634716

申请日：2017-06-27

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed M. Elsayed

IPC: H03K17/16

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.

公开(公告)号：US20190094079A1

公开(公告)日：2019-03-28

申请号：US15717924

申请日：2017-09-27

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed M. Elsayed ,  Kenneth W. Fernald

IPC: G01K7/02 ,  H03K5/24 ,  G05F1/56

CPC classification number: G01K7/02 ,  G01K7/01 ,  G01K2219/00 ,  G05F1/56 ,  G05F3/30 ,  H03K5/24

Abstract: An apparatus includes a temperature measurement circuit. The temperature measurement circuit includes a bandgap circuit including an amplifier having an offset voltage that is compensated by using a set of trimming bits. The bandgap circuit provides first and second voltages related to a temperature to be measured. The temperature measurement circuit further includes a measuring circuit coupled to receive the first and second voltages. The measuring circuit further includes a comparator coupled to receive the first and second voltages, wherein the measuring circuit derives a temperature measurement from the first and second voltages.

公开(公告)号：US20190051366A1

公开(公告)日：2019-02-14

申请号：US15676757

申请日：2017-08-14

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed M. Elsayed

IPC: G11C27/02 ,  H03K17/687

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches.