Invention Grant
- Patent Title: Semiconductor package with improved thermal blocks
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Application No.: US16639049Application Date: 2017-09-29
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Publication No.: US11652074B2Publication Date: 2023-05-16
- Inventor: Feras Eid , Johanna Swan
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP.
- International Application: PCT/US2017/054584 2017.09.29
- International Announcement: WO2019/066957A 2019.04.04
- Date entered country: 2020-02-13
- Main IPC: G11C5/06
- IPC: G11C5/06 ; H01L27/108 ; H01L21/02 ; H01L21/56 ; H01L21/762 ; H01L23/31 ; H01L23/00 ; H01L23/498 ; H01L29/417 ; H01L29/66 ; H01L29/78 ; H01L21/768 ; H01L29/40 ; H01L21/285 ; H01L29/49 ; H01L23/532 ; H01L25/065

Abstract:
An apparatus is provided which comprises: a first set of one or more metal pads on a first substrate surface, the first set of one or more metal pads to couple with contacts of an integrated circuit die, a second set of one or more metal pads on the first substrate surface, the second set of one or more metal pads to couple with semiconductor surfaces of the integrated circuit die, one or more thermal regions below the first substrate surface, wherein the one or more thermal regions comprise thermally conductive material and are coupled with the second set of one or more metal pads, dielectric material adjacent the one or more thermal regions, and one or more conductive contacts on a second substrate surface, opposite the first substrate surface, the one or more conductive contacts coupled with the first set of one or more metal pads, and the one or more conductive contacts to couple with contacts of a printed circuit board. Other embodiments are also disclosed and claimed.
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