公开(公告)号：US12155372B2

公开(公告)日：2024-11-26

申请号：US17688065

申请日：2022-03-07

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H03H9/54 ,  H03H9/02 ,  H03H9/64

Abstract: Embodiments may relate to a die such as an acoustic wave resonator (AWR) die. The die may include a first filter and a second filter in the die body. The die may further include an electromagnetic interference (EMI) structure that surrounds at least one of the filters. Other embodiments may be described or claimed.

公开(公告)号：US12113048B2

公开(公告)日：2024-10-08

申请号：US18090801

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Feras Eid ,  Johanna M. Swan ,  Shawna M. Liff

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L24/17 ,  H01L24/24 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/1703 ,  H01L2224/17135 ,  H01L2224/17136 ,  H01L2224/17177 ,  H01L2224/17181 ,  H01L2224/24146 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.

公开(公告)号：US20240274576A1

公开(公告)日：2024-08-15

申请号：US18632919

申请日：2024-04-11

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel A. Elsherbini ,  Aleksandar Aleksov ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/17 ,  H01L24/29 ,  H01L24/30 ,  H01L25/0652 ,  H01L2224/08225 ,  H01L2224/09177 ,  H01L2224/81

Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region including metal contacts that are distributed non-uniformly. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact.

公开(公告)号：US12040776B2

公开(公告)日：2024-07-16

申请号：US16526633

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Aleksandar Aleksov ,  Feras Eid ,  Georgios Dogiamis ,  Johanna M. Swan

IPC: H03H9/05 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18 ,  H03H9/58 ,  H10N30/87 ,  H10N30/88 ,  H10N39/00 ,  H01L23/498

CPC classification number: H03H9/0552 ,  H01L23/5385 ,  H01L24/16 ,  H01L25/18 ,  H01L25/50 ,  H03H9/58 ,  H10N30/875 ,  H10N30/883 ,  H10N39/00 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2924/19042

Abstract: Embodiments may relate to a radio frequency (RF) front-end module (FEM) that includes an acoustic wave resonator (AWR) die. The RF FEM may further include an active die coupled with the package substrate of the RF FEM. When the active die is coupled with the package substrate, the AWR die may be between the active die and the package substrate. Other embodiments may be described or claimed.

公开(公告)号：US12002745B2

公开(公告)日：2024-06-04

申请号：US17544693

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew J. Manusharow ,  Krishna Bharath ,  William J. Lambert ,  Robert L. Sankman ,  Aleksandar Aleksov ,  Brandon M. Rawlings ,  Feras Eid ,  Javier Soto Gonzalez ,  Meizi Jiao ,  Suddhasattwa Nad ,  Telesphor Kamgaing

IPC: H05K1/02 ,  H01F17/00 ,  H01F17/06 ,  H01F27/28 ,  H01F27/40 ,  H01F41/04 ,  H01G4/18 ,  H01G4/252 ,  H01G4/30 ,  H01G4/33 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H01L23/66 ,  H01L49/02

CPC classification number: H01L23/49838 ,  H01F17/0006 ,  H01F27/2804 ,  H01F27/40 ,  H01F41/041 ,  H01G4/33 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/66 ,  H01L28/00 ,  H01L28/10 ,  H01L28/60 ,  H01F2027/2809 ,  H01L2223/6661

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

公开(公告)号：US20240063178A1

公开(公告)日：2024-02-22

申请号：US17821001

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Adel A. Elsherbini ,  Xavier Francois Brun ,  Kimin Jun ,  Shawna M. Liff ,  Johanna M. Swan ,  Yi Shi ,  Tushar Talukdar ,  Feras Eid ,  Mohammad Enamul Kabir ,  Omkar G. Karhade ,  Bhaskar Jyoti Krishnatreya

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/3107 ,  H01L24/16 ,  H01L24/08 ,  H01L2225/06548 ,  H01L2224/16227 ,  H01L2224/08145 ,  H01L2224/13116 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13109 ,  H01L2224/13118 ,  H01L24/13 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05613 ,  H01L2224/05609 ,  H01L2224/05605 ,  H01L24/05

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die and a through-dielectric via (TDV) surrounded by a dielectric material in a first layer, where the TDV has a greater width at a first surface and a smaller width at an opposing second surface of the first layer; a second die, surrounded by the dielectric material, in a second layer on the first layer, where the first die is coupled to the second die by interconnects having a pitch of less than 10 microns, and the dielectric material around the second die has an interface seam extending from a second surface of the second layer towards an opposing first surface of the second layer with an angle of less than 90 degrees relative to the second surface; and a substrate on and coupled to the second layer.

公开(公告)号：US20240063143A1

公开(公告)日：2024-02-22

申请号：US17891690

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Lance C. Hibbeler ,  Omkar Karhade ,  Chytra Pawashe ,  Kimin Jun ,  Feras Eid ,  Shawna Liff ,  Mohammad Enamul Kabir ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Wenhao Li

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L25/0657 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2924/3511

Abstract: Techniques and mechanisms to mitigate warping of a composite chiplet. In an embodiment, multiple via structures each extend through an insulator material in one of multiple levels of a composite chiplet. The insulator material extends around an integrated circuit (IC) component in the level. For a given one of the multiple via structures, a respective annular structure extends around the via structure to mitigate a compressive (or tensile) stress due to expansion (or contraction) of the via structure. In another embodiment, the composite chiplet additionally or alternatively comprises a structural support layer on the multiple levels, wherein the structural support layer has formed therein or thereon dummy via structures or a warpage compensation film.

公开(公告)号：US20240063142A1

公开(公告)日：2024-02-22

申请号：US17891666

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Wenhao Li ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Botao Zhang ,  Yi Shi ,  Haris Khan Niazi ,  Feras Eid ,  Nagatoshi Tsunoda ,  Xavier Brun ,  Mohammad Enamul Kabir ,  Omkar Karhade ,  Shawna Liff ,  Jiraporn Seangatith

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L23/367 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L21/486 ,  H01L21/565 ,  H01L25/0655 ,  H01L25/50

Abstract: Multi-die packages including IC die crack mitigation features. Prior to the bonding of IC dies to a host substrate, the IC dies may be shaped, for example with a corner radius or chamfer. After bonding the shaped IC dies, a fill comprising at least one inorganic material may be deposited over the IC dies, for example to backfill a space between adjacent IC dies. With the benefit of a greater IC die sidewall slope and/or smoother surface topology associated with the shaping process, occurrences of stress cracking within the fill and concomitant damage to the IC dies may be reduced. Prior to depositing a fill, a barrier layer may be deposited over the IC die to prevent cracks that might form in the fill material from propagating into the IC die.

公开(公告)号：US20240063133A1

公开(公告)日：2024-02-22

申请号：US17891536

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Beomseok Choi ,  Feras Eid ,  Omkar Karhade ,  Shawna Liff

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/5386 ,  H01L24/08 ,  H01L24/80 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/0652 ,  H01L23/3128 ,  H01L21/56 ,  H01L21/4853 ,  H01L2924/1434 ,  H01L2924/1432 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/08225 ,  H01L2224/08145

Abstract: A multichip composite device includes on- and off-die metallization layers, inorganic dielectric material, and stacked hybrid-bonded dies. On-die metallization layers may be thinner than off-die metallization layers. The multichip composite device may include a structural substrate. Off-die metallization layers may be above and below the stacked hybrid-bonded dies. A substrate may couple the multichip composite device to a power supply in a multichip system. Forming a multichip composite device includes hybrid bonding dies and forming inorganic dielectric material.

公开(公告)号：US20240063089A1

公开(公告)日：2024-02-22

申请号：US17891738

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Wenhao Li ,  Bhaskar Jyoti Krishnatreya ,  Debendra Mallik ,  Krishna Vasanth Valavala ,  Lei Jiang ,  Yoshihiro Tomita ,  Omkar Karhade ,  Haris Khan Niazi ,  Tushar Talukdar ,  Mohammad Enamul Kabir ,  Xavier Brun ,  Feras Eid

IPC: H01L23/46

CPC classification number: H01L23/46 ,  G02B6/4268

Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die and an inorganic dielectric material adjacent the integrated circuit dies and over the base die. The multichip composite device includes a dummy die, dummy vias, or integrated fluidic cooling channels laterally adjacent the integrated circuit dies to conduct heat from the base die.