公开(公告)号：US20250112196A1

公开(公告)日：2025-04-03

申请号：US18478843

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Feras Eid ,  Johanna Swan ,  Adel Elsherbini ,  Thomas L. Sounart ,  Tushar Kanti Talukdar ,  Brandon M. Rawlings ,  Kimin Jun ,  Andrey Vyatskikh ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L23/373 ,  H01L23/38 ,  H01L23/433 ,  H01L23/538 ,  H10N19/00

Abstract: An embodiment discloses an electronic device, comprising an integrated circuit (IC) die, a mesa structure formed on the IC die, and a die bonded to the IC die through the mesa structure.

公开(公告)号：US20250112067A1

公开(公告)日：2025-04-03

申请号：US18478963

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Thomas L. Sounart ,  Feras Eid ,  Tushar Kanti Talukdar ,  Adel Elsherbini ,  Carlos Bedoya Arroyave ,  Johanna Swan

IPC: H01L21/67 ,  H01L21/56 ,  H01L21/683 ,  H01L21/762

Abstract: In one embodiment, a selective transfer process includes forming a layer of integrated circuit (IC) components on a first substrate. The method also includes dispensing liquid droplets into a subset of a plurality of areas of a second substrate, where the areas of the second substrate are defined by hydrophobic lines patterned to match a layout of the IC components on the first substrate. The method further includes partially bonding the first substrate to the second substrate, where a subset of the IC components on the first substrate are bonded to the liquid droplets on the second substrate (e.g., via capillary forces), and separating the first substrate from the second substrate. When the first substrate is separated from the second substrate, the subset of IC components is separated from the first substrate and remain on the second substrate.

公开(公告)号：US11694986B2

公开(公告)日：2023-07-04

申请号：US17500824

申请日：2021-10-13

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Patrick Morrow ,  Johanna Swan ,  Shawna Liff ,  Mauro Kobrinksy ,  Van Le ,  Gerald Pasdast

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L25/18 ,  H01L25/00 ,  H01L21/768 ,  H01L21/82 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L24/24 ,  H01L21/76898 ,  H01L21/82 ,  H01L23/481 ,  H01L23/528 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/24147 ,  H01L2224/24155

Abstract: A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet.

公开(公告)号：US11664303B2

公开(公告)日：2023-05-30

申请号：US17375360

申请日：2021-07-14

Applicant: Intel Corporation

Inventor： Johanna Swan ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong

IPC: H01L23/498 ,  G03F1/38 ,  G03F1/54 ,  G03F1/68

CPC classification number: H01L23/49838 ,  G03F1/38 ,  G03F1/54 ,  G03F1/68 ,  H01L23/49827 ,  H01L23/49866

Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.

公开(公告)号：US20230098020A1

公开(公告)日：2023-03-30

申请号：US17484384

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Feras Eid ,  Aleksandar Aleksov ,  Henning Braunisch ,  Adel Elsherbini ,  Thomas L. Sounart ,  Johanna Swan

IPC: H01L23/473 ,  H01L23/50 ,  H05K7/20 ,  H01L23/31

Abstract: Technologies for cooling conformal power delivery structures are disclosed. In one embodiment, an integrated circuit component has a die with a backside power plane mated to it. A lid of the integrated circuit component is mated with the backside power plane, forming a sealed cavity. The lid has an inlet and an outlet, and a channel is defined in the lid for liquid coolant to flow from the inlet, across the backside power plane, and to the outlet. The liquid coolant directly contacts the backside power plane, efficiently removing heat from the backside power plane.

公开(公告)号：US20230095654A1

公开(公告)日：2023-03-30

申请号：US17484213

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Stephen Morein ,  Krishna Bharath ,  Henning Braunisch ,  Beomseok Choi ,  Brandon M. Rawlings ,  Thomas L. Sounart ,  Johanna Swan ,  Yoshihiro Tomita ,  Aleksandar Aleksov

IPC: H01L23/498 ,  H01L23/48 ,  H01L25/065 ,  H01L21/48

Abstract: In one embodiment, a conformal power delivery structure includes a first electrically conductive layer comprising metal. The first electrically conductive layer defines one or more recesses, and the conformal power delivery structure also includes a second electrically conductive layer comprising metal that is at least partially within the recesses of the first electrically conductive layer. The second electrically conductive layer has a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure further includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

公开(公告)号：US11594801B2

公开(公告)日：2023-02-28

申请号：US16613070

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Sasha Oster ,  Telesphor Kamgaing ,  Erich Ewy ,  Kenneth Shoemaker ,  Adel Elsherbini ,  Johanna Swan

IPC: B60R11/04 ,  H01P3/16 ,  B60R16/023 ,  B60W40/02

Abstract: Embodiments of the invention include autonomous vehicles and mm-wave systems for communication between components. In an embodiment the vehicle includes an electronic control unit (ECU). The ECU may include a printed circuit board (PCB) and a CPU die packaged on a CPU packaging substrate. In an embodiment, the CPU packaging substrate is electrically coupled to the PCB. The ECU may also include an external predefined interface electrically coupled to the CPU die. In an embodiment, an active mm-wave interconnect may include a dielectric waveguide, and a first connector coupled to a first end of the dielectric waveguide. In an embodiment, the first connector comprises a first mm-wave engine, and the first connector is electrically coupled to the external predefined interface. Embodiments may also include a second connector coupled to a second end of the dielectric waveguide, wherein the second connector comprises a second mm-wave engine.

公开(公告)号：US20220415837A1

公开(公告)日：2022-12-29

申请号：US17359380

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Feras Eid ,  Adel Elsherbini ,  Aleksandar Aleksov ,  Shawna Liff ,  Johanna Swan ,  Julien Sebot

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00

Abstract: Techniques and mechanisms for mitigating stress on hybrid bonded interfaces in a multi-tier arrangement of integrated circuit (IC) dies. In an embodiment, first dies are bonded at a host die each via a respective one of first hybrid bond interfaces, wherein a second one or more dies are coupled to the host die each via a respective one of the first dies, and via a respective second hybrid bond interface. Stress at one of the hybrid bond interfaces is mitigated by properties of a first dielectric layer that extends to that hybrid bond interface. In another embodiment, stress at a given one of the hybrid bond interfaces is mitigated by properties of a dummy chip—or alternatively, properties of a patterned encapsulation structure—which is formed on the given hybrid bond interface.

公开(公告)号：US11462810B2

公开(公告)日：2022-10-04

申请号：US17194022

申请日：2021-03-05

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Sasha Oster ,  Georgios Dogiamis ,  Johanna Swan

IPC: H01P5/08 ,  H01P1/207 ,  H01P3/12

Abstract: Embodiments of the invention include a mm-wave waveguide connector and methods of forming such devices. In an embodiment the mm-wave waveguide connector may include a plurality of mm-wave launcher portions, and a plurality of ridge based mm-wave filter portions each communicatively coupled to one of the mm-wave launcher portions. In an embodiment, the ridge based mm-wave filter portions each include a plurality of protrusions that define one or more resonant cavities. Additional embodiments may include a multiplexer portion communicatively coupled to the plurality of ridge based mm-wave filter portions and communicative coupled to a mm-wave waveguide bundle. In an embodiment the plurality of protrusions define resonant cavities with openings between 0.5 mm and 2.0 mm, the plurality of protrusions are spaced apart from each other by a spacing between 0.5 mm and 2.0 mm, and wherein the plurality of protrusions have a thickness between 200 μm and 1,000 μm.

公开(公告)号：US11460499B2

公开(公告)日：2022-10-04

申请号：US16573946

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Aleksandar Aleksov ,  Veronica Strong ,  Brandon Rawlings ,  Johanna Swan ,  Shawna Liff

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  G01R31/28 ,  G01K7/42 ,  G01K7/02

Abstract: An integrated circuit package having an electronic interposer comprising an upper section, a lower section and a middle section, a die side integrated circuit device electrically attached to the upper section of the electronic interposer, a die side heat dissipation device thermally contacting the die side integrated circuit device, a land side integrated circuit device electrically attached to the lower section of the electronic interposer, and a land side heat dissipation device thermally contacting the at least one die side integrated circuit device. The upper section and the lower section may each have between two and four layers and the middle section may be formed between the upper section and the lower section, and comprises up to eight layers, wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and the lower section.