Invention Grant
- Patent Title: Solid state thermoelectric cooler in silicon backend layers for fast cooling in turbo scenarios
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Application No.: US16665621Application Date: 2019-10-28
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Publication No.: US11664293B2Publication Date: 2023-05-30
- Inventor: Krishna Vasanth Valavala , Ravindranath V. Mahajan , Chandra Mohan Jha
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L23/38
- IPC: H01L23/38 ; H01L23/42 ; H01L23/367 ; H01L23/10 ; H01L21/48 ; H01L25/065 ; H01L23/00

Abstract:
Embodiments include a semiconductor package with a thermoelectric cooler (TEC), a method to form such semiconductor package, and a semiconductor packaged system. The semiconductor package includes a die with a plurality of backend layers on a package substrate. The backend layers couple the die to the package substrate. The semiconductor package includes the TEC in the backend layers of the die. The TEC includes a plurality of N-type layers, a plurality of P-type layers, and first and second conductive layers. The first conductive layer is directly coupled to outer regions of bottom surfaces of the N-type and P-type layers, and the second conductive layer is directly coupled to inner regions of top surfaces of the N-type and P-type layers. The first conductive layer has a width greater than a width of the second conductive layer. The N-type and P-type layers are directly disposed between the first and second conductive layers.
Public/Granted literature
- US20210125897A1 SOLID STATE THERMOELECTRIC COOLER IN SILICON BACKEND LAYERS FOR FAST COOLING IN TURBO SCENARIOS Public/Granted day:2021-04-29
Information query
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