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公开(公告)号：US20240063089A1
公开(公告)日：2024-02-22
申请号：US17891738
申请日：2022-08-19
Applicant: Intel Corporation
Inventor： Adel Elsherbini , Wenhao Li , Bhaskar Jyoti Krishnatreya , Debendra Mallik , Krishna Vasanth Valavala , Lei Jiang , Yoshihiro Tomita , Omkar Karhade , Haris Khan Niazi , Tushar Talukdar , Mohammad Enamul Kabir , Xavier Brun , Feras Eid
IPC: H01L23/46
CPC classification number: H01L23/46 , G02B6/4268
Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die and an inorganic dielectric material adjacent the integrated circuit dies and over the base die. The multichip composite device includes a dummy die, dummy vias, or integrated fluidic cooling channels laterally adjacent the integrated circuit dies to conduct heat from the base die.
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公开(公告)号：US11756856B2
公开(公告)日：2023-09-12
申请号：US16149909
申请日：2018-10-02
Applicant: Intel Corporation
Inventor： Krishna Vasanth Valavala , Ravindranath Mahajan , Chandra Mohan Jha , Kelly Lofgreen , Weihua Tang
CPC classification number: H01L23/373 , H01L23/3114 , H01L23/38 , H01L25/18 , H01L29/43 , H10N10/17
Abstract: Embodiments include a microelectronic device package structure having a first die on the substrate. One or more additional dice are on the first die, and a thermal electric cooler (TEC) is on the first die adjacent at least one of the one or more additional dice. A dummy die is on the TEC, wherein the dummy die is thermally coupled to the first die.
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公开(公告)号：US11462457B2
公开(公告)日：2022-10-04
申请号：US16142366
申请日：2018-09-26
Applicant: Intel Corporation
Inventor： Krishna Vasanth Valavala , Kelly Lofgreen , Chandra-Mohan Jha
IPC: H01L23/38 , H01L21/48 , H01L23/367 , H01L25/065
Abstract: Embodiments herein relate to systems, apparatuses, processing, and techniques related to a first heat-conducting plate to be thermally coupled to a first heat source, a thermoelectric cooler (TEC) thermally coupled to the first plate, a second heat-conducting plate thermally coupled to the TEC and to be thermally coupled to a second heat source where the TEC is to at least partially thermally isolate the first plate from the second plate to reduce heat transfer from the first plate to the second plate.
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公开(公告)号：US20200312742A1
公开(公告)日：2020-10-01
申请号：US16370703
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Kelly Lofgreen , Chandra Mohan Jha , Krishna Vasanth Valavala
Abstract: An IC package, comprising a first IC component comprising a first interconnect on a first surface thereof; a second IC component comprising a second interconnect on a second surface thereof. The second component is above the first component, and the second surface is opposite the first surface. A thermoelectric cooling (TEC) device is between the first surface and the second surface. The TEC device is electrically coupled to the first interconnect and to the second interconnect.
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公开(公告)号：US20240063076A1
公开(公告)日：2024-02-22
申请号：US17891727
申请日：2022-08-19
Applicant: Intel Corporation
Inventor： Mohammad Enamul Kabir , Bhaskar Jyoti Krishnatreya , Kimin Jun , Adel Elsherbini , Tushar Talukdar , Feras Eid , Debendra Mallik , Krishna Vasanth Valavala , Xavier Brun
IPC: H01L23/367 , H01L23/00 , H01L23/373 , H01L23/48 , H01L25/065
CPC classification number: H01L23/367 , H01L24/08 , H01L23/3736 , H01L23/373 , H01L23/3732 , H01L23/481 , H01L24/32 , H01L24/29 , H01L25/0657 , H01L2224/08145 , H01L2224/32225 , H01L2224/29147 , H01L2224/29124 , H01L2224/29139 , H01L2224/29144 , H01L2224/29193 , H01L2224/29186
Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die, a conformal thermal heat spreading layer on the top and sidewalls of the integrated circuit dies, and an inorganic dielectric material on a portion of the conformal thermal heat spreading layer, laterally adjacent the integrated circuit dies, and over the base die. The conformal thermal heat spreading layer includes a high thermal conductivity material to provide a thermal pathway for the integrated circuit dies during operation.
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Patent Agency Ranking
公开(公告)号：US20230290706A1
公开(公告)日：2023-09-14
申请号：US17693003
申请日：2022-03-11
Applicant: Intel Corporation
Inventor： Gaurav Patankar , Shankar Devasenathipathy , Krishna Vasanth Valavala
IPC: H01L23/427 , H01L23/367 , H01L23/473
CPC classification number: H01L23/427 , H01L23/3672 , H01L23/473
Abstract: A surplus liquid reservoir attached to a vapor chamber integrated heat spreader (IHS) and placed near a heat source on a heterogenous die. The vapor chamber integrated heat spreader (IHS) includes a main heat transfer portion that encloses a vapor channel, a first wick material, and a first working fluid. The surplus liquid reservoir is provided by a reservoir leg mechanically coupled, on a first side, to the main heat transfer portion, the reservoir leg has a reservoir portion with a second working fluid and second wick material that is in contact with the first wick material. The surplus liquid reservoir can either support a PL2 that is higher than a given vapor chamber Qmax for a significantly long time or increase the PL2 value to a significantly higher value.
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公开(公告)号：US11658095B2
公开(公告)日：2023-05-23
申请号：US16370703
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Kelly Lofgreen , Chandra Mohan Jha , Krishna Vasanth Valavala
CPC classification number: H01L23/38 , H01L23/481 , H01L24/09 , H01L24/17 , H01L25/18 , H10N10/01 , H10N10/82 , H01L2924/1434
Abstract: An IC package, comprising a first IC component comprising a first interconnect on a first surface thereof; a second IC component comprising a second interconnect on a second surface thereof. The second component is above the first component, and the second surface is opposite the first surface. A thermoelectric cooling (TEC) device is between the first surface and the second surface. The TEC device is electrically coupled to the first interconnect and to the second interconnect.
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公开(公告)号：US20200312741A1
公开(公告)日：2020-10-01
申请号：US16362961
申请日：2019-03-25
Applicant: Intel Corporation
Inventor： Zhimin Wan , Krishna Vasanth Valavala , Chandra Mohan Jha , Shankar Devasenathipathy
IPC: H01L23/38 , H01L23/373 , H01L35/32
Abstract: An IC package comprising a substrate comprising a dielectric, an IC device coupled to the substrate; and a thermoelectric cooling (TEC) device adjacent to the IC device and coupled to the substrate. A thermal trace extends laterally on or within the dielectric between the TEC device to the IC device, and the thermal trace is coupled to the TEC device and the IC device.
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9.发明公开公开(公告)号：US20240063183A1
公开(公告)日：2024-02-22
申请号：US17820982
申请日：2022-08-19
Applicant: Intel Corporation
Inventor： Adel A. Elsherbini , Kaladhar Radhakrishnan , Anne Augustine , Beomseok Choi , Kimin Jun , Omkar G. Karhade , Shawna M. Liff , Julien Sebot , Johanna M. Swan , Krishna Vasanth Valavala
IPC: H01L25/065 , H01L23/00 , H01L23/538 , H01L23/48
CPC classification number: H01L25/0655 , H01L24/08 , H01L24/16 , H01L23/5381 , H01L23/5386 , H01L24/80 , H01L23/481 , H01L2224/16225 , H01L2224/08145 , H01L2924/3512 , H01L2924/3841 , H01L2924/37001 , H01L2924/1427 , H01L2924/1431 , H01L2924/1434 , H01L2224/80895 , H01L2224/80896
Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of monolithic wafers and disaggregated integrated circuit (IC) dies, adjacent layers being coupled together by first interconnects having a pitch less than 10 micrometers between adjacent first interconnects, the disaggregated IC dies arranged with portions of the monolithic wafers into modular sub-assemblies; and a package substrate coupled to the modular sub-assemblies by second interconnects having a pitch greater than 10 micrometers between adjacent second interconnects. The disaggregated IC dies are surrounded laterally by a dielectric material, and the disaggregated IC dies are arranged with portions of the monolithic wafers such that a voltage regulator circuit in a first layer of the plurality of layers, a compute circuit in a second layer of the plurality of layers, and a memory circuit in a third layer of the plurality of layers are conductively coupled together in an intra-modular power delivery circuitry.
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公开(公告)号：US20240063179A1
公开(公告)日：2024-02-22
申请号：US17821009
申请日：2022-08-19
Applicant: Intel Corporation
Inventor： Adel A. Elsherbini , Krishna Vasanth Valavala , Kimin Jun , Shawna M. Liff , Johanna M. Swan , Debendra Mallik , Feras Eid , Xavier Francois Brun , Bhaskar Jyoti Krishnatreya
IPC: H01L25/065 , H01L25/00 , H01L23/00 , H01L21/56
CPC classification number: H01L25/0652 , H01L25/50 , H01L24/20 , H01L24/08 , H01L21/568 , H01L24/19 , H01L24/06 , H01L2224/221 , H01L2224/211 , H01L2224/08225 , H01L2224/19 , H01L2224/0612 , H01L2224/06181 , H01L24/13 , H01L2224/13025 , H01L24/16 , H01L2224/16227 , H01L2924/381
Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a dielectric layer having one or more conductive traces and a surface; a microelectronic subassembly on the surface of the dielectric layer, the microelectronic subassembly including a first die and a through-dielectric via (TDV) surrounded by a dielectric material, wherein the first die is at the surface of the dielectric layer; a second die and a third die on the first die and electrically coupled to the first die by interconnects having a pitch of less than 10 microns, and wherein the TDV is electrically coupled at a first end to the dielectric layer and at an opposing second end to the second die; and a substrate on and coupled to the second and third dies; and an insulating material on the surface of the dielectric layer and around the microelectronic subassembly.
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