Invention Grant
- Patent Title: Glitch suppression apparatus and method
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Application No.: US17152901Application Date: 2021-01-20
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Publication No.: US11687428B2Publication Date: 2023-06-27
- Inventor: Avneep Kumar Goyal
- Applicant: STMicroelectronics International N.V.
- Applicant Address: CH Geneva
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: CH Geneva
- Agency: Slater Matsil, LLP
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/263 ; G06F1/06 ; G06F11/22

Abstract:
An apparatus includes a main core processor configured to receive a first signal through a first main buffer, a second signal through a second main buffer, a third signal through a third main buffer and a fourth signal through a fourth main buffer, a shadow core processor configured to receive the first signal through a first shadow buffer, the second signal through a second shadow buffer, the third signal through a third shadow buffer and the fourth signal through a fourth shadow buffer, and a first glitch suppression buffer coupled to a common node of an input of the first main buffer and an input of the first shadow buffer.
Public/Granted literature
- US20220229752A1 GLITCH SUPPRESSION APPARATUS AND METHOD Public/Granted day:2022-07-21
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