A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal; and a third register field to store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal. The memory device also includes second and third registers to store values for selecting one of the plurality of CA ODT impedance values and one of the plurality of CS ODT impedance values for application to the first inputs and second input, respectively.