Invention Grant
- Patent Title: Stacked structure for a vertical memory device
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Application No.: US17347652Application Date: 2021-06-15
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Publication No.: US11700731B2Publication Date: 2023-07-11
- Inventor: Il-Woo Kim , Sang-Ho Rha , Byoung-Deog Choi , Ik-Soo Kim , Min-Jae Oh
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si
- Agency: Lee IP Law, P.C.
- Priority: KR 20180130092 2018.10.29
- Main IPC: H10B43/27
- IPC: H10B43/27 ; H01L21/28 ; H01L21/67 ; H01L21/8234 ; H10B43/35

Abstract:
A method of manufacturing a vertical memory device includes forming a first sacrificial layer on a substrate, the first sacrificial layer including a first insulating material, forming a mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer, the insulation layer and the second sacrificial layer including second and third insulating materials, respectively, different from the first insulating material, forming a channel through the mold and the first sacrificial layer, forming an opening through the mold and the first sacrificial layer to expose an upper surface of the substrate, removing the first sacrificial layer through the opening to form a first gap, forming a channel connecting pattern to fill the first gap, and replacing the second sacrificial layer with a gate electrode.
Public/Granted literature
- US20210313347A1 STACKED STRUCTURE FOR A VERTICAL MEMORY DEVICE Public/Granted day:2021-10-07
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