公开(公告)号：US11063060B2

公开(公告)日：2021-07-13

申请号：US16454499

申请日：2019-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il-Woo Kim ,  Sang-Ho Rha ,  Byoung-Deog Choi ,  Ik-Soo Kim ,  Min-Jae Oh

IPC: H01L21/8234 ,  H01L21/67 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/28

Abstract: A method of manufacturing a vertical memory device includes forming a first sacrificial layer on a substrate, the first sacrificial layer including a first insulating material, forming a mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer, the insulation layer and the second sacrificial layer including second and third insulating materials, respectively, different from the first insulating material, forming a channel through the mold and the first sacrificial layer, forming an opening through the mold and the first sacrificial layer to expose an upper surface of the substrate, removing the first sacrificial layer through the opening to form a first gap, forming a channel connecting pattern to fill the first gap, and replacing the second sacrificial layer with a gate electrode.

公开(公告)号：US11133317B2

公开(公告)日：2021-09-28

申请号：US16420387

申请日：2019-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun-Won Lee ,  Hyuk-Woo Kwon ,  Ik-Soo Kim ,  Byoung-Deog Choi

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/8234

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including a substrate; a lower structure including pad patterns on the substrate, upper surfaces of the pad patterns being at an outer side of the lower structure; a plurality of lower electrodes contacting the upper surfaces of the pad patterns; a dielectric layer and an upper electrode sequentially stacked on a surface of each of the lower electrodes; and a hydrogen supply layer including hydrogen, the hydrogen supply layer being between the lower electrodes and closer to the substrate than the dielectric layer is to the substrate.

公开(公告)号：US09953928B2

公开(公告)日：2018-04-24

申请号：US15185384

申请日：2016-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-Rae Kim ,  Byoung-Deog Choi ,  Hee-Young Park ,  Sang-Ho Roh ,  Jin-Hyung Park ,  Kyung-Mun Byun

IPC: H01L21/764 ,  H01L23/532 ,  H01L29/06 ,  H01L27/108 ,  H01L23/535

CPC classification number: H01L23/5329 ,  H01L21/764 ,  H01L23/535 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L29/0649

Abstract: Semiconductor devices including empty spaces and methods of forming the semiconductor devices are provided. The semiconductor devices may include first and second line structures extending in a direction on a substrate, an insulating isolation pattern between the first and second line structures and a conductive structure between the first and second line structures and next to the insulating isolation pattern along the direction. The semiconductor devices may also include an empty space including a first portion between the first line structure and the conductive structure and a second portion between the first line structure and the insulating isolation pattern. The first portion of the empty space may have a height different from a height of the second portion of the empty space.

公开(公告)号：US11737256B2

公开(公告)日：2023-08-22

申请号：US17476663

申请日：2021-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun-Won Lee ,  Hyuk-Woo Kwon ,  Ik-Soo Kim ,  Byoung-Deog Choi

IPC: H10B12/00 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H10B12/03 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02131 ,  H01L21/02164 ,  H01L21/311 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823468 ,  H10B12/0335 ,  H10B12/30

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including a substrate; a lower structure including pad patterns on the substrate, upper surfaces of the pad patterns being at an outer side of the lower structure; a plurality of lower electrodes contacting the upper surfaces of the pad patterns; a dielectric layer and an upper electrode sequentially stacked on a surface of each of the lower electrodes; and a hydrogen supply layer including hydrogen, the hydrogen supply layer being between the lower electrodes and closer to the substrate than the dielectric layer is to the substrate.

公开(公告)号：US11700731B2

公开(公告)日：2023-07-11

申请号：US17347652

申请日：2021-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il-Woo Kim ,  Sang-Ho Rha ,  Byoung-Deog Choi ,  Ik-Soo Kim ,  Min-Jae Oh

IPC: H10B43/27 ,  H01L21/28 ,  H01L21/67 ,  H01L21/8234 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/67178 ,  H01L21/823487 ,  H01L29/40117 ,  H10B43/35 ,  H01L2924/1438

Abstract: A method of manufacturing a vertical memory device includes forming a first sacrificial layer on a substrate, the first sacrificial layer including a first insulating material, forming a mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer, the insulation layer and the second sacrificial layer including second and third insulating materials, respectively, different from the first insulating material, forming a channel through the mold and the first sacrificial layer, forming an opening through the mold and the first sacrificial layer to expose an upper surface of the substrate, removing the first sacrificial layer through the opening to form a first gap, forming a channel connecting pattern to fill the first gap, and replacing the second sacrificial layer with a gate electrode.

公开(公告)号：US09391138B2

公开(公告)日：2016-07-12

申请号：US14274002

申请日：2014-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-Rae Kim ,  Byoung-Deog Choi ,  Hee-Young Park ,  Sang-Ho Roh ,  Jin-Hyung Park ,  Kyung-Mun Byun

IPC: H01L29/06 ,  H01L21/764 ,  H01L27/108

CPC classification number: H01L23/5329 ,  H01L21/764 ,  H01L23/535 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L29/0649

Abstract: Semiconductor devices including empty spaces and methods of forming the semiconductor devices are provided. The semiconductor devices may include first and second line structures extending in a direction on a substrate, an insulating isolation pattern between the first and second line structures and a conductive structure between the first and second line structures and next to the insulating isolation pattern along the direction. The semiconductor devices may also include an empty space including a first portion between the first line structure and the conductive structure and a second portion between the first line structure and the insulating isolation pattern. The first portion of the empty space may have a height different from a height of the second portion of the empty space.

Abstract translation: 提供包括空白空间的半导体器件和形成半导体器件的方法。 半导体器件可以包括沿着衬底上的方向延伸的第一和第二线结构，在第一和第二线结构之间的绝缘隔离图案以及在第一和第二线结构之间的导电结构，并且沿绝缘隔离图案沿着方向 。 半导体器件还可以包括空白空间，其包括第一线结构和导电结构之间的第一部分和第一线结构与绝缘隔离图案之间的第二部分。 空白空间的第一部分可以具有与空白空间的第二部分的高度不同的高度。