公开(公告)号：US11063060B2

公开(公告)日：2021-07-13

申请号：US16454499

申请日：2019-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il-Woo Kim ,  Sang-Ho Rha ,  Byoung-Deog Choi ,  Ik-Soo Kim ,  Min-Jae Oh

IPC: H01L21/8234 ,  H01L21/67 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/28

Abstract: A method of manufacturing a vertical memory device includes forming a first sacrificial layer on a substrate, the first sacrificial layer including a first insulating material, forming a mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer, the insulation layer and the second sacrificial layer including second and third insulating materials, respectively, different from the first insulating material, forming a channel through the mold and the first sacrificial layer, forming an opening through the mold and the first sacrificial layer to expose an upper surface of the substrate, removing the first sacrificial layer through the opening to form a first gap, forming a channel connecting pattern to fill the first gap, and replacing the second sacrificial layer with a gate electrode.

公开(公告)号：US11233494B2

公开(公告)日：2022-01-25

申请号：US16593376

申请日：2019-10-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungjoon Kim ,  Je-Dong Lee ,  Younghoon Kwon ,  Myoungwoon Kim ,  Il-Woo Kim ,  Jiwoon Im ,  Jaewon Jung ,  Hee Jong Jeong

IPC: H03H7/01 ,  H01J37/32

Abstract: An electronic circuit includes a first filter and a second filter. The first filter passes a first frequency component of a first harmonic frequency generated by a first voltage source to form a potential difference in a chamber and a second frequency component of a second harmonic frequency higher than the first harmonic frequency. The second filter removes the first frequency component and the second frequency component received from the first filter. The second harmonic frequency is included in a first frequency band determined based on a capacitance of the second filter.

公开(公告)号：US11700731B2

公开(公告)日：2023-07-11

申请号：US17347652

申请日：2021-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il-Woo Kim ,  Sang-Ho Rha ,  Byoung-Deog Choi ,  Ik-Soo Kim ,  Min-Jae Oh

IPC: H10B43/27 ,  H01L21/28 ,  H01L21/67 ,  H01L21/8234 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/67178 ,  H01L21/823487 ,  H01L29/40117 ,  H10B43/35 ,  H01L2924/1438

Abstract: A method of manufacturing a vertical memory device includes forming a first sacrificial layer on a substrate, the first sacrificial layer including a first insulating material, forming a mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer, the insulation layer and the second sacrificial layer including second and third insulating materials, respectively, different from the first insulating material, forming a channel through the mold and the first sacrificial layer, forming an opening through the mold and the first sacrificial layer to expose an upper surface of the substrate, removing the first sacrificial layer through the opening to form a first gap, forming a channel connecting pattern to fill the first gap, and replacing the second sacrificial layer with a gate electrode.

公开(公告)号：US11348938B2

公开(公告)日：2022-05-31

申请号：US16446028

申请日：2019-06-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il-Woo Kim ,  Sang-Gi An ,  Hyun-Gon Pyo ,  Ik-Soo Kim ,  Hee-Sook Park ,  Ji-Woon Im

IPC: H01L21/336 ,  H01L27/11582 ,  H01L21/311 ,  H01L27/11565

Abstract: In a method of manufacturing a vertical memory device, a first sacrificial layer including a nitride is formed on a substrate. A mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer is formed. The insulation layer and the second sacrificial layer include a first oxide and a second oxide, respectively. A channel is formed through the mold and the first sacrificial layer. An opening is formed through the mold and the first sacrificial layer to expose an upper surface of the substrate. The first sacrificial layer is removed through the opening to form a first gap. A channel connecting pattern is formed to fill the first gap. The second sacrificial layer is replaced with a gate electrode.

公开(公告)号：US09299826B2

公开(公告)日：2016-03-29

申请号：US14204441

申请日：2014-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hauk Han ,  Il-Woo Kim ,  Jeong-Gil Lee ,  Yong-Il Kwon ,  Myoung-Bum Lee

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L27/115 ,  H01L21/768

CPC classification number: H01L29/78 ,  H01L21/76805 ,  H01L21/76831 ,  H01L27/11529 ,  H01L29/66825

Abstract: A memory device includes a gate structure, a contact plug, and a spacer. The gate structure includes first and second conductive layer patterns sequentially stacked on a substrate. The contact plug passes through the second conductive layer pattern, and a sidewall of the contact plug directly contacts at least a portion of the second conductive layer pattern. The spacer surrounds a portion of the sidewall of the contact plug and contacting the gate structure.

Abstract translation: 存储器件包括栅极结构，接触插塞和间隔物。 栅极结构包括顺序地堆叠在衬底上的第一和第二导电层图案。 接触插塞穿过第二导电层图案，并且接触插塞的侧壁直接接触第二导电层图案的至少一部分。 间隔件围绕接触塞的侧壁的一部分并接触门结构。