Invention Grant
- Patent Title: Stacked die cavity package
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Application No.: US17720202Application Date: 2022-04-13
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Publication No.: US11705377B2Publication Date: 2023-07-18
- Inventor: Mitul Modi , Robert L. Sankman , Debendra Mallik , Ravindranath V. Mahajan , Amruthavalli P. Alur , Yikang Deng , Eric J. Li
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- The original application number of the division: US16463638
- Main IPC: H01L23/13
- IPC: H01L23/13 ; H01L21/48 ; H01L21/56 ; H01L23/31 ; H01L23/498 ; H01L25/065 ; H01L25/18 ; H01L25/00 ; H01L23/00

Abstract:
An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.
Public/Granted literature
- US20220238402A1 STACKED DIE CAVITY PACKAGE Public/Granted day:2022-07-28
Information query
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