Invention Grant
- Patent Title: Mitigating a voltage condition of a memory cell in a memory sub-system
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Application No.: US17868685Application Date: 2022-07-19
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Publication No.: US11710527B2Publication Date: 2023-07-25
- Inventor: Vamsi Pavan Rayaprolu , Kishore Kumar Muchherla , Peter Feeley , Sampath K. Ratnam , Sivagnanam Parthasarathy , Qisong Lin , Shane Nowell , Mustafa N. Kaynak
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- The original application number of the division: US16045641 2018.07.25
- Main IPC: G11C16/34
- IPC: G11C16/34 ; G11C16/10 ; G11C16/14 ; G11C29/00 ; G06F11/07 ; G11C16/26 ; G06F3/06 ; G11C16/04

Abstract:
A determination that a first programming operation has been performed on a particular memory cell can be made. A determination can be made, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.
Public/Granted literature
- US20220351786A1 MITIGATING A VOLTAGE CONDITION OF A MEMORY CELL IN A MEMORY SUB-SYSTEM Public/Granted day:2022-11-03
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