Invention Grant
- Patent Title: Semiconductor device package including stress buffering layer
-
Application No.: US17330240Application Date: 2021-05-25
-
Publication No.: US11721678B2Publication Date: 2023-08-08
- Inventor: Chien-Mei Huang , Shih-Yu Wang , I-Ting Lin , Wen Hung Huang , Yuh-Shan Su , Chih-Cheng Lee , Hsing Kuo Tien
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaohsiung
- Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee Address: TW Kaohsiung
- Agency: Foley & Lardner LLP
- Main IPC: H01L25/16
- IPC: H01L25/16 ; H01L23/31 ; H01L23/00 ; H01L23/522 ; H01L21/56 ; H01L23/528 ; H01L23/29

Abstract:
A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.
Public/Granted literature
- US20210280565A1 SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2021-09-09
Information query
IPC分类: