Invention Grant
- Patent Title: Interconnect structure and method of forming same
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Application No.: US17073533Application Date: 2020-10-19
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Publication No.: US11728296B2Publication Date: 2023-08-15
- Inventor: Hsiao Yun Lo , Lin-Chih Huang , Tasi-Jung Wu , Hsin-Yu Chen , Yung-Chi Lin , Ku-Feng Yang , Tsang-Jiuh Wu , Wen-Chih Chiou
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- The original application number of the division: US14158364 2014.01.17
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/48

Abstract:
A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.
Public/Granted literature
- US20210050316A1 Interconnect Structure and Method of Forming Same Public/Granted day:2021-02-18
Information query
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