公开(公告)号：US20200343176A1

公开(公告)日：2020-10-29

申请号：US16927249

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chi Lin ,  Hsin-Yu Chen ,  Lin-Chih Huang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/528 ,  H01L27/088 ,  H01L23/31 ,  H01L23/48 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768

Abstract: A method comprises forming a trench extending through an interlayer dielectric layer over a substrate and partially through the substrate, depositing a photoresist layer over the trench, wherein the photoresist layer partially fills the trench, patterning the photoresist layer to remove the photoresist layer in the trench and form a metal line trench over the interlayer dielectric layer, filling the trench and the metal line trench with a conductive material to form a via and a metal line, wherein an upper portion of the trench is free of the conductive material and depositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the trench.

公开(公告)号：US20210050316A1

公开(公告)日：2021-02-18

申请号：US17073533

申请日：2020-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao Yun Lo ,  Lin-Chih Huang ,  Tasi-Jung Wu ,  Hsin-Yu Chen ,  Yung-Chi Lin ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/00 ,  H01L23/48

Abstract: A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.

公开(公告)号：US11756883B2

公开(公告)日：2023-09-12

申请号：US16927249

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chi Lin ,  Hsin-Yu Chen ,  Lin-Chih Huang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/528 ,  H01L27/088 ,  H01L23/31 ,  H01L23/48 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768 ,  H01L23/525

CPC classification number: H01L23/528 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/53238 ,  H01L24/13 ,  H01L27/088 ,  H01L23/525 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53271 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/0557 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2224/05572 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00

Abstract: A method comprises forming a trench extending through an interlayer dielectric layer over a substrate and partially through the substrate, depositing a photoresist layer over the trench, wherein the photoresist layer partially fills the trench, patterning the photoresist layer to remove the photoresist layer in the trench and form a metal line trench over the interlayer dielectric layer, filling the trench and the metal line trench with a conductive material to form a via and a metal line, wherein an upper portion of the trench is free of the conductive material and depositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the trench.

公开(公告)号：US11728296B2

公开(公告)日：2023-08-15

申请号：US17073533

申请日：2020-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao Yun Lo ,  Lin-Chih Huang ,  Tasi-Jung Wu ,  Hsin-Yu Chen ,  Yung-Chi Lin ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0391 ,  H01L2224/03462 ,  H01L2224/03602 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05565 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/1145 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/131 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2224/05187 ,  H01L2924/04941 ,  H01L2224/05187 ,  H01L2924/04953 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/05181 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05184 ,  H01L2924/00014 ,  H01L2224/05139 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/013 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2924/00014 ,  H01L2224/03602 ,  H01L2924/00014 ,  H01L2224/03614 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/1145 ,  H01L2924/00014 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014

Abstract: A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.