- 专利标题: Method of forming a semiconductor device structure having an isolation layer to isolate a conductive feature and a gate electrode layer
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申请号: US17459379申请日: 2021-08-27
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公开(公告)号: US11756995B2公开(公告)日: 2023-09-12
- 发明人: Lung-Kun Chu , Mao-Lin Huang , Chung-Wei Hsu , Jia-Ni Yu , Kuan-Lun Cheng , Kuo-Cheng Chiang , Chih-Hao Wang
- 申请人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 申请人地址: TW Hsinchu
- 专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人地址: TW Hsinchu
- 代理机构: NZ Carr Law Office
- 主分类号: H01L29/06
- IPC分类号: H01L29/06 ; H01L21/8234 ; H01L29/775 ; H01L21/8238 ; H01L21/822 ; H01L27/06 ; H01L27/088 ; H01L27/092 ; H01L29/08
摘要:
A semiconductor device structure, along with methods of forming such, are described. The structure includes first and second dielectric features and a first semiconductor layer disposed between the first and second dielectric features. The structure further includes an isolation layer disposed between the first and second dielectric features, and the isolation layer is in contact with the first and second dielectric features. The first semiconductor layer is disposed over the isolation layer. The structure further includes a gate dielectric layer disposed over the isolation layer and a gate electrode layer disposed over the gate dielectric layer. The gate electrode layer has an end extending to a level between a first plane defined by a first surface of the first semiconductor layer and a second plane defined by a second surface opposite the first surface.
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