发明授权
- 专利标题: Corner guard for improved electroplated first level interconnect bump height range
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申请号: US16511376申请日: 2019-07-15
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公开(公告)号: US11776864B2公开(公告)日: 2023-10-03
- 发明人: Jacob Vehonsky , Nicholas S. Haehn , Thomas Heaton , Steve S. Cho , Rahul Jain , Tarek Ibrahim , Antariksh Rao Pratap Singh , Edvin Cetegen , Nicholas Neal , Sergio Chan Arguedas
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwabe, Williamson & Wyatt P.C.
- 主分类号: H01L23/16
- IPC分类号: H01L23/16 ; H01L23/498 ; H01L23/367 ; H01L23/00
摘要:
Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.
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