公开(公告)号：US20220285079A1

公开(公告)日：2022-09-08

申请号：US17192187

申请日：2021-03-04

申请人： Intel Corporation

发明人： Srinivas Pietambaram ,  Pooya Tadayon ,  Kristof Darmawikarta ,  Tarek Ibrahim ,  Prithwish Chatterjee

IPC分类号： H01F27/28 ,  H01F1/04 ,  H01F27/40 ,  H05K1/16

摘要： An inductor can be formed in a coreless electronic substrate from magnetic materials and/or fabrication processes that do not result in the magnetic materials leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming the inductors from magnetic ferrites. The formation of the electronic substrates may also include process sequences that prevent exposure of the magnetic ferrites to the plating and/or etching solutions/chemistries.

公开(公告)号：US20220093520A1

公开(公告)日：2022-03-24

申请号：US17026703

申请日：2020-09-21

申请人： Intel Corporation

发明人： Jeremy D. Ecton ,  Aleksandar Aleksov ,  Brandon C. Marin ,  Yonggang Li ,  Leonel Arana ,  Suddhasattwa Nad ,  Haobo Chen ,  Tarek Ibrahim

IPC分类号： H01L23/538 ,  H05K1/11 ,  H01L21/768

摘要： Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.

公开(公告)号：US12057252B2

公开(公告)日：2024-08-06

申请号：US17029870

申请日：2020-09-23

申请人： Intel Corporation

发明人： Benjamin Duong ,  Michael Garelick ,  Darko Grujicic ,  Tarek Ibrahim ,  Brandon C. Marin ,  Sai Vadlamani ,  Marcel Wall

IPC分类号： H05K1/02 ,  H01F1/37 ,  H01F17/04 ,  H01F17/06 ,  H01F27/24 ,  H01F27/245 ,  H01F27/28 ,  H01F27/29 ,  H01F41/24 ,  H01F41/32 ,  H01L23/15 ,  H01L23/498 ,  H01L23/64 ,  H05K1/09 ,  H05K3/02 ,  H05K3/42

CPC分类号： H01F27/2804 ,  H01F41/32 ,  H01L23/49827 ,  H01L23/645 ,  H01F2027/2809 ,  H01L23/49816

摘要： An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.

公开(公告)号：US12009271B2

公开(公告)日：2024-06-11

申请号：US16511360

申请日：2019-07-15

申请人： Intel Corporation

发明人： Edvin Cetegen ,  Jacob Vehonsky ,  Nicholas S. Haehn ,  Thomas Heaton ,  Steve S. Cho ,  Rahul Jain ,  Tarek Ibrahim ,  Antariksh Rao Pratap Singh ,  Nicholas Neal ,  Sergio Chan Arguedas ,  Vipul Mehta

IPC分类号： H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/16 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/18161

摘要： Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

公开(公告)号：US20240327201A1

公开(公告)日：2024-10-03

申请号：US18192576

申请日：2023-03-29

申请人： Intel Corporation

发明人： Numair Ahmed ,  Mohammad Mamunur Rahman ,  Suddhasattwa Nad ,  Sashi Kandanur ,  Darko Grujicic ,  Benjamin Duong ,  Srinivas Pietambaram ,  Tarek Ibrahim ,  Whitney Bryks

IPC分类号： B81B7/00 ,  B81C1/00 ,  G02B6/12

CPC分类号： B81B7/0048 ,  B81C1/00325 ,  G02B6/12004 ,  B81B2201/0228 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/0278 ,  B81B2201/03 ,  B81B2201/045 ,  B81B2207/07 ,  B81B2207/096 ,  B81B2207/097

摘要： MEMS dies embedded in glass cores of integrated circuit (IC) package substrates are disclosed. An example integrated circuit (IC) package includes a package substrate including a glass core, the example integrated circuit (IC) package also includes a micro electromechanical system (MEMS) die positioned in a cavity of the glass core.

公开(公告)号：US11776864B2

公开(公告)日：2023-10-03

申请号：US16511376

申请日：2019-07-15

申请人： Intel Corporation

发明人： Jacob Vehonsky ,  Nicholas S. Haehn ,  Thomas Heaton ,  Steve S. Cho ,  Rahul Jain ,  Tarek Ibrahim ,  Antariksh Rao Pratap Singh ,  Edvin Cetegen ,  Nicholas Neal ,  Sergio Chan Arguedas

IPC分类号： H01L23/16 ,  H01L23/498 ,  H01L23/367 ,  H01L23/00

CPC分类号： H01L23/16 ,  H01L23/3675 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/10152 ,  H01L2224/11011 ,  H01L2224/11462 ,  H01L2224/16227 ,  H01L2924/381

摘要： Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.

公开(公告)号：US11764150B2

公开(公告)日：2023-09-19

申请号：US16502025

申请日：2019-07-03

申请人： Intel Corporation

发明人： Sri Chaitra Jyotsna Chavali ,  Tarek Ibrahim ,  Wei-Lun Jen

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H05K1/18 ,  H01L23/48 ,  H01L23/64

CPC分类号： H01L23/5227 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/645 ,  H01L28/10 ,  H05K1/181 ,  H05K2201/1003

摘要： Embodiments herein describe techniques for a semiconductor device including a package substrate having a core layer. An inductor may include a first coaxial line and a second coaxial line vertically through the core layer, and an interconnect within the package substrate coupling the first coaxial line and the second coaxial line. A first magnetic segment may surround the first coaxial line within the core layer, and a second magnetic segment may surround the second coaxial line within the core layer. In addition, a third magnetic segment may surround the interconnect and be coupled to the first magnetic segment and the second magnetic segment. Other embodiments may be described and/or claimed.

公开(公告)号：US20220093316A1

公开(公告)日：2022-03-24

申请号：US17029870

申请日：2020-09-23

申请人： Intel Corporation

发明人： Benjamin Duong ,  Michael Garelick ,  Darko Grujicic ,  Tarek Ibrahim ,  Brandon C. Marin ,  Sai Vadlamani ,  Marcel Wall

IPC分类号： H01F27/28 ,  H01L23/64 ,  H01F41/32 ,  H01L23/498

摘要： An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.

公开(公告)号：US20210273036A1

公开(公告)日：2021-09-02

申请号：US16804317

申请日：2020-02-28

申请人： Intel Corporation

发明人： Brandon C. Marin ,  Tarek Ibrahim ,  Prithwish Chatterjee ,  Haifa Hariri ,  Yikang Deng ,  Sheng C. Li ,  Srinivas Pietambaram

IPC分类号： H01L49/02 ,  H05K1/18 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

摘要： An integrated circuit (IC) package substrate, comprising a magnetic material embedded within a dielectric material. A first surface of the dielectric material is below the magnetic material, and a second surface of the dielectric material, opposite the first surface, is over the magnetic material. A metallization level comprising a first metal feature is embedded within the magnetic material. A second metal feature is at an interface of the magnetic material and the dielectric material. The second metal feature has a first sidewall in contact with the dielectric material and a second sidewall in contact with the magnetic material.

公开(公告)号：US12033930B2

公开(公告)日：2024-07-09

申请号：US17033392

申请日：2020-09-25

申请人： Intel Corporation

发明人： Jieying Kong ,  Yiyang Zhou ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Hongxia Feng ,  Tarek Ibrahim ,  Brandon Marin ,  Zhiguo Qian ,  Sarah Blythe ,  Bohan Shan ,  Jason Steill ,  Sri Chaitra Jyotsna Chavali ,  Leonel Arana ,  Dingying Xu ,  Marcel Wall

IPC分类号： H01L23/498 ,  H01L21/48

CPC分类号： H01L23/49838 ,  H01L21/485 ,  H01L23/49827

摘要： An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.