公开(公告)号：US12154715B2

公开(公告)日：2024-11-26

申请号：US17873518

申请日：2022-07-26

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Kyu-Oh Lee ,  Junnan Zhao ,  Rahul Jain ,  Ji Yong Park ,  Sai Vadlamani ,  Seo Young Kim

IPC: H01F27/28 ,  H01F27/02 ,  H01F27/24 ,  H05K1/18

Abstract: Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.

公开(公告)号：US12009271B2

公开(公告)日：2024-06-11

申请号：US16511360

申请日：2019-07-15

Applicant: Intel Corporation

Inventor： Edvin Cetegen ,  Jacob Vehonsky ,  Nicholas S. Haehn ,  Thomas Heaton ,  Steve S. Cho ,  Rahul Jain ,  Tarek Ibrahim ,  Antariksh Rao Pratap Singh ,  Nicholas Neal ,  Sergio Chan Arguedas ,  Vipul Mehta

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/16 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/18161

Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

公开(公告)号：US11737208B2

公开(公告)日：2023-08-22

申请号：US16268813

申请日：2019-02-06

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Andrew James Brown ,  Rahul Jain ,  Dilan Seneviratne ,  Praneeth Kumar Akkinepally ,  Frank Truong

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H01L23/498

CPC classification number: H05K1/0228 ,  H01L23/49822 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface, wherein the substrate layer includes a photo-imageable dielectric (PID) and an electroless catalyst; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the first thickness is greater than the second thickness.

公开(公告)号：US11652071B2

公开(公告)日：2023-05-16

申请号：US17158634

申请日：2021-01-26

Applicant: Intel Corporation

Inventor： Brandon C Marin ,  Shivasubramanian Balasubramanian ,  Rahul Jain ,  Praneeth Akkinepally ,  Jeremy D Ecton

IPC: H01L23/495 ,  H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L21/48

CPC classification number: H01L23/642 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L28/40

Abstract: A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.

公开(公告)号：US11355459B2

公开(公告)日：2022-06-07

申请号：US15982652

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： Kyu-Oh Lee ,  Sai Vadlamani ,  Rahul Jain ,  Junnan Zhao ,  Ji Yong Park ,  Cheng Xu ,  Seo Young Kim

IPC: H01L23/60 ,  H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01F1/12 ,  H01F41/14

Abstract: Techniques for fabricating a semiconductor package having magnetic materials embedded therein are described. For one technique, fabrication of package includes: forming a pad and a conductive line on a build-up layer; forming a raised pad structure on the build-up layer, the raised pad comprising a pillar structure on the pad; encapsulating the conductive line and the raised pad structure in a magnetic film comprising one or more magnetic fillers; planarizing a top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar; depositing a primer layer on the top surfaces; removing one or more portions of the primer layer above the raised pad structure to create an opening; and forming a via in the opening on the raised pad structure. The primer layer may comprise one or more of a build-up layer, a photoimageable dielectric layer, and a metal mask.

公开(公告)号：US11139264B2

公开(公告)日：2021-10-05

申请号：US16586820

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Rahul Jain ,  Ji Yong Park ,  Kyu Oh Lee

IPC: H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065

Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

公开(公告)号：US10468374B2

公开(公告)日：2019-11-05

申请号：US15475175

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Rahul Jain ,  Ji Yong Park ,  Kyu Oh Lee

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

公开(公告)号：US12224264B2

公开(公告)日：2025-02-11

申请号：US18385167

申请日：2023-10-30

Applicant: Intel Corporation

Inventor： Rahul Jain ,  Ji Yong Park ,  Kyu Oh Lee

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

公开(公告)号：US11901115B2

公开(公告)日：2024-02-13

申请号：US17873509

申请日：2022-07-26

Applicant: Intel Corporation

Inventor： Kyu-Oh Lee ,  Rahul Jain ,  Sai Vadlamani ,  Cheng Xu ,  Ji Yong Park ,  Junnan Zhao ,  Seo Young Kim

IPC: H01F27/32 ,  H01L23/498 ,  H01F41/04 ,  H01L21/48 ,  H01F27/28 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01F27/327 ,  H01F27/2804 ,  H01F41/043 ,  H01L21/486 ,  H01L21/4857 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/49838 ,  H01F2027/2809 ,  H01L21/6835 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16227 ,  H01L2224/16267 ,  H01L2924/19042 ,  H01L2924/19102

Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.

公开(公告)号：US11776864B2

公开(公告)日：2023-10-03

申请号：US16511376

申请日：2019-07-15

Applicant: Intel Corporation

Inventor： Jacob Vehonsky ,  Nicholas S. Haehn ,  Thomas Heaton ,  Steve S. Cho ,  Rahul Jain ,  Tarek Ibrahim ,  Antariksh Rao Pratap Singh ,  Edvin Cetegen ,  Nicholas Neal ,  Sergio Chan Arguedas

IPC: H01L23/16 ,  H01L23/498 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/16 ,  H01L23/3675 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/10152 ,  H01L2224/11011 ,  H01L2224/11462 ,  H01L2224/16227 ,  H01L2924/381

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.