Invention Grant
- Patent Title: Corner guard for improved electroplated first level interconnect bump height range
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Application No.: US16511376Application Date: 2019-07-15
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Publication No.: US11776864B2Publication Date: 2023-10-03
- Inventor: Jacob Vehonsky , Nicholas S. Haehn , Thomas Heaton , Steve S. Cho , Rahul Jain , Tarek Ibrahim , Antariksh Rao Pratap Singh , Edvin Cetegen , Nicholas Neal , Sergio Chan Arguedas
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- Main IPC: H01L23/16
- IPC: H01L23/16 ; H01L23/498 ; H01L23/367 ; H01L23/00

Abstract:
Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.
Public/Granted literature
- US20210020532A1 CORNER GUARD FOR IMPROVED ELECTROPLATED FIRST LEVEL INTERCONNECT BUMP HEIGHT RANGE Public/Granted day:2021-01-21
Information query
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