Invention Grant
- Patent Title: Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths
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Application No.: US17335994Application Date: 2021-06-01
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Publication No.: US11776877B2Publication Date: 2023-10-03
- Inventor: Sameer S. Vadhavkar , Xiao Li , Steven K. Groothuis , Jian Li , Jaspreet S. Gandhi , James M. Derderian , David R. Hembree
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- The original application number of the division: US16020567 2018.06.27
- Main IPC: H01L23/44
- IPC: H01L23/44 ; H01L25/00 ; H01L21/56 ; H01L23/00 ; H01L23/367 ; H01L25/18 ; H01L23/04 ; H01L21/50 ; H01L25/065 ; H01L23/373 ; H01L21/52 ; H01L21/54 ; H01L23/053 ; H01L23/31

Abstract:
Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.
Public/Granted literature
- US20220013434A1 METHODS OF MANUFACTURING STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS Public/Granted day:2022-01-13
Information query
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