- 专利标题： Vertical transistors for ultra-dense logic and memory applications
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申请号： US16455567申请日： 2019-06-27
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公开(公告)号： US11777029B2公开(公告)日： 2023-10-03
- 发明人: Nazila Haratipour , I-Cheng Tung , Abhishek A. Sharma , Arnab Sen Gupta , Van Le , Matthew V. Metz , Jack Kavalieros , Tahir Ghani
- 申请人： Intel Corporation
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Essential Patents Group, LLP
- 主分类号： H01L29/78
- IPC分类号： H01L29/78 ; H01L29/423 ; H01L29/66
摘要：
A vertical transistor structure includes a material stack having a source material, a drain material, and a channel material therebetween. The vertical transistor structure further includes a gate electrode adjacent to a sidewall of the stack, where the sidewall includes the channel material, and at least a partial thickness of both the source material and the drain material. A gate dielectric is present between the sidewall of the stack and the gate electrode. The vertical transistor structure further includes a first metallization over a first area of the stack above the gate dielectric layer, and in contact with the gate electrode on sidewall of the stack. A second metallization is adjacent to the first metallization, where the second metallization is over a second area of the stack, and in contact with the source material or the drain material.
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