Invention Grant
- Patent Title: Spacer-defined process for lithography-etch double patterning for interconnects
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Application No.: US17484347Application Date: 2021-09-24
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Publication No.: US11804401B2Publication Date: 2023-10-31
- Inventor: Nelson Felix , Ekmini Anuja De Silva , Luciana Meli Thompson , Yann Mignot
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Amin, Turocy & Watson, LLP
- The original application number of the division: US16174666 2018.10.30
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/027 ; H01L21/033 ; H01L21/3105 ; H01L21/311

Abstract:
One or more embodiments described herein include systems, and/or methods that facilitate fabrication of a semiconductor device using a spacer lithography-etch process. According to an embodiment, a method can comprise performing a first lithography exposure and etch over a first layer of a semiconductor device, where the first lithography exposure and etch comprises forming one or more mandrels on a first region of a second layer by employing a first photoresist layer. The method can further comprise forming one or more spacers on a sidewall of the one or more mandrels and covering a second region of the second layer, where the second region is adjacent to the one or more mandrels. The method can further comprise forming a cut over a third region of the second layer and filling the third region with first material.
Public/Granted literature
- US20220013405A1 SPACER-DEFINED PROCESS FOR LITHOGRAPHY-ETCH DOUBLE PATTERNING FOR INTERCONNECTS Public/Granted day:2022-01-13
Information query
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