公开(公告)号：US20240419882A1

公开(公告)日：2024-12-19

申请号：US18333685

申请日：2023-06-13

Applicant: International Business Machines Corporation

Inventor： Xiaoming Yang ,  SOMNATH GHOSH ,  Huai Huang ,  Yann Mignot ,  Kai Zhao ,  Daniel Charles Edelstein

IPC: G06F30/39

Abstract: Embodiments of the invention are directed to a computer system having a processor communicatively coupled to a memory. The processor performs processor operations that include accessing an electronic file that includes an electronic integrated circuit (IC) design. The electronic file is operable to control a fabrication system to fabricate an IC according to the electronic IC design. The processor operations further includes applying a bulging predication analysis to the electronic IC design; and making one or more changes to the electronic IC design based at least in part on a result of the bulging prediction analysis.

公开(公告)号：US12010930B2

公开(公告)日：2024-06-11

申请号：US17470003

申请日：2021-09-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Injo Ok ,  Hsueh-Chung Chen ,  Mary Claire Silvestre ,  Yann Mignot

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/828 ,  H10N70/026 ,  H10N70/231 ,  H10N70/823 ,  H10N70/8828

Abstract: A semiconductor structure includes a plurality of conductive lines formed within a dielectric, wherein each of the plurality of conductive lines electrically communicates with a respective contact, a metal layer disposed over each of the plurality of conductive lines, a phase change memory (PCM) element disposed over the metal layer of each of the plurality of conductive lines, and a projection liner encapsulating the PCM element. Spacers directly contact sidewalls of the projection liner and the PCM element includes a GeSbTe (germanium-antimony-tellurium or GST) layer.

公开(公告)号：US20240188447A1

公开(公告)日：2024-06-06

申请号：US18062380

申请日：2022-12-06

Applicant: International Business Machines Corporation

Inventor： Chanro Park ,  Koichi Motoyama ,  Hsueh-Chung Chen ,  Yann Mignot ,  Daniel Worledge

IPC: H10N50/01 ,  G11C11/16 ,  H10B61/00 ,  H10N50/80

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L27/222 ,  H01L43/02

Abstract: A memory structure including a magnetic tunnel junction (MTJ) structure and a top electrode that are both formed without utilizing ion beam etching is provided. The MTJ structure, which includes a lower magnetic stack, a tunnel barrier layer and an upper magnetic stack, is pyramidal shaped, and end portions of the lower magnetic stack of the MTJ structure are devoid of the tunnel barrier layer and the upper magnetic stack.

公开(公告)号：US20240153865A1

公开(公告)日：2024-05-09

申请号：US17980617

申请日：2022-11-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yann Mignot ,  Koichi Motoyama ,  Hsueh-Chung Chen ,  Chanro Park

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76885 ,  H01L23/5221 ,  H01L23/53266

Abstract: A semiconductor structure is presented including a first level of interconnect wiring and a second level of interconnect wiring having a bilayer metal arrangement incorporating via elements, the second level of interconnect wiring electrically connected to the first level of interconnect wiring. In one example, the bilayer metal arrangement of the second level of interconnect wiring includes a first row of bilayer metals and a second row of bilayer metals disposed over the first row of bilayer metals. In another example, the bilayer metal arrangement of the second level of interconnect wiring includes a cap dielectric material for isolation from the first row of the bilayer metal. In yet another embodiment, the bilayer metal arrangement of the second level of interconnect wiring includes a metal bridge.

公开(公告)号：US20240099148A1

公开(公告)日：2024-03-21

申请号：US17932691

申请日：2022-09-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Koichi Motoyama ,  Chanro Park ,  Yann Mignot ,  Chih-Chao Yang

IPC: H01L43/12 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor device is provided. The semiconductor device includes a memory including a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and an upper electrode on the MTJ stack. The semiconductor device also includes at least one dielectric layer formed around the memory, wherein a top metal layer contact hole is formed in the at least one dielectric layer, a dielectric liner layer formed in the top metal contact hole, and a top metal layer contact in the top metal layer contact hole.

公开(公告)号：US20230411477A1

公开(公告)日：2023-12-21

申请号：US17807873

申请日：2022-06-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Su Chen Fan ,  Nicolas Jean Loubet ,  Yann Mignot ,  Tsung-Sheng Kang ,  Eric Miller

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/45 ,  H01L29/417

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/41775 ,  H01L29/458 ,  H01L29/78696

Abstract: A gate-all-around transistor structure including a channel region surrounded on three sides by a gate conductor, and a pair of salicide regions extending from opposite ends of the channel region in a direction parallel with the gate conductor.

公开(公告)号：US11784120B2

公开(公告)日：2023-10-10

申请号：US17480824

申请日：2021-09-21

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  James J. Kelly ,  Muthumanickam Sankarapandian ,  Yongan Xu ,  Hsueh-Chung Chen ,  Daniel J. Vincent

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L23/5226 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5283 ,  H01L21/0276

Abstract: A semiconductor device includes a stack structure having at least first, second and third interconnect levels. Each interconnect level has a patterned metal conductor including a first metallic material. A via spans the second and third interconnect levels and electrically couples with the patterned metal conductor of the first interconnect level. At least a segment of the super via includes a second metallic material different from the first metallic material.

公开(公告)号：US20230171114A1

公开(公告)日：2023-06-01

申请号：US17537605

申请日：2021-11-30

Applicant: International Business Machines Corporation

Inventor： Dallas Lea ,  Yann Mignot ,  Marc A. Bergendahl ,  Alex Joseph Varghese ,  Sean Teehan ,  Andrew M. Greene ,  Matthew T. Shoudy

IPC: H04L9/32 ,  H03K3/03 ,  H03H7/06 ,  H03H7/01 ,  H03K3/037

CPC classification number: H04L9/3278 ,  H03K3/0315 ,  H03H7/06 ,  H03H7/0161 ,  H03K3/037

Abstract: A physical unclonable function (PUF) device includes a ring oscillator, a plurality of band-pass filters, a demultiplexer, and a latch. The ring oscillator generates a frequency signal. Each passive band-pass filter performs filtering on the frequency signal to pass the frequency signal or block the frequency signal. The demultiplexer receives a set of challenge bits and delivers the frequency signal to a selected passive band-pass filter among the plurality of passive band-passed filters based on the challenge bit. The latch outputs a response bit in response to the filtering performed by the selected passive band-pass filter.

公开(公告)号：US20230138978A1

公开(公告)日：2023-05-04

申请号：US17453010

申请日：2021-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： CHANRO PARK ,  Chi-Chun LIU ,  Stuart Sieg ,  Yann Mignot ,  Koichi Motoyama ,  Hsueh-Chung Chen

IPC: H01L21/033 ,  H01L21/3213

Abstract: A method of semiconductor manufacture comprising forming a plurality of first mandrels as the top layer of the multi-layered hard mask and forming a first spacer around each of the plurality of first mandrels. Removing the plurality of first mandrels and cutting the first spacer to form a plurality of second mandrels. Forming a second spacer around each of the plurality of second mandrels and forming a first self-aligned pattern that includes a plurality of third mandrels. Removing the plurality of second mandrels and the second spacer and etching the multi-layered hard mask to transfer the first-self aligned pattern to a lower layer of the multi-layered hard mask. Forming a second self-aligned pattern, wherein the second self-aligned pattern is intermixed with the first self-aligned pattern and etching the first self-aligned pattern and the second self-aligned pattern into the conductive metal layer.

公开(公告)号：US20230100368A1

公开(公告)日：2023-03-30

申请号：US17483922

申请日：2021-09-24

Applicant: International Business Machines Corporation

Inventor： Hsueh-Chung Chen ,  Yann Mignot ,  Su Chen Fan ,  Mary Claire Silvestre ,  Chi-Chun LIU ,  Junli Wang

IPC: H01L23/522 ,  H01L21/768

Abstract: A device includes: a first dielectric material; a first metal line in the first dielectric material; a second dielectric material disposed on the first dielectric material and the first metal line; a second metal line in the second dielectric material; and a plurality of metal vias disposed on a same level and connecting the first metal line and the second metal line, wherein the plurality of metal vias comprise a first top via and a bottom via having different sidewall profile angles.