Invention Grant
- Patent Title: Wafer level passive heat spreader interposer to enable improved thermal solution for stacked dies in multi-chips package and warpage control
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Application No.: US16548255Application Date: 2019-08-22
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Publication No.: US11804470B2Publication Date: 2023-10-31
- Inventor: Xavier F. Brun , Kaizad Mistry , Paul R. Start , Nisha Ananthakrishnan , Yawei Liang , Jigneshkumar P. Patel , Sairam Agraharam , Liwei Wang
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L25/00 ; H01L23/367 ; H01L23/29 ; H01L23/31 ; H01L23/00 ; H01L25/18 ; H01L23/48 ; H01L21/56

Abstract:
Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.
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