Invention Grant
- Patent Title: Chip assemblies
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Application No.: US17089736Application Date: 2020-11-05
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Publication No.: US11805602B2Publication Date: 2023-10-31
- Inventor: Loke Yip Foo , Choong Kooi Chee , Teong Guan Yew
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: VIERING,JENTSCHURA&PARTNER MBB
- Priority: MY 2020004594 2020.09.04
- Main IPC: H05K1/18
- IPC: H05K1/18 ; H01L23/498 ; H01L23/00 ; H01L23/538 ; H05K3/34 ; H05K3/32

Abstract:
A chip assembly may include a package substrate that includes one or more pins. The chip assembly may also include one or more pads. The one or more pads may be electrically coupled to the one or more pins. In addition, the chip assembly may include a board that includes one or more board pads. Further, the chip assembly may include an anisotropic layer. The anisotropic layer may be positioned between the board and the one or more pads and between the board and a portion of the package substrate. In addition, the anisotropic layer may mechanically couple the board to the one or more pads and to the portion of the package substrate. Further, the anisotropic layer may electrically couple the one or more pads to the one or more board pads.
Public/Granted literature
- US20220078914A1 CHIP ASSEMBLIES Public/Granted day:2022-03-10
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