公开(公告)号：US12237245B2

公开(公告)日：2025-02-25

申请号：US18089207

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Loke Yip Foo ,  Choong Kooi Chee

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L25/18

Abstract: Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.

公开(公告)号：US11562959B2

公开(公告)日：2023-01-24

申请号：US16912638

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Loke Yip Foo ,  Teong Guan Yew ,  Choong Kooi Chee

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A dual-sided embedded multi-die interconnect bridge provides power and source conduits from the bridge bottom at a silicon portion, in short paths to dice on a die side of an integrated-circuit package substrate. Signal traces are in a metallization on the silicon portion of the dual-sided EMIB. Power, ground and signal vias all emanate from the dual-sided embedded multi-die interconnect bridge, with power and ground entering the bridge from central regions of the silicon portion.

公开(公告)号：US11107751B2

公开(公告)日：2021-08-31

申请号：US16284239

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Loke Yip Foo ,  Choong Kooi Chee

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31 ,  H01L23/538 ,  H01L23/367 ,  H01L21/56

Abstract: Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.

公开(公告)号：US20190304876A1

公开(公告)日：2019-10-03

申请号：US16284239

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Loke Yip Foo ,  Choong Kooi Chee

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31 ,  H01L23/538 ,  H01L23/367 ,  H01L21/56

Abstract: Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.

公开(公告)号：US11805602B2

公开(公告)日：2023-10-31

申请号：US17089736

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Loke Yip Foo ,  Choong Kooi Chee ,  Teong Guan Yew

IPC: H05K1/18 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H05K3/34 ,  H05K3/32

CPC classification number: H05K1/181 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H05K3/323 ,  H05K3/3436 ,  H01L2224/16225 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2201/10992

Abstract: A chip assembly may include a package substrate that includes one or more pins. The chip assembly may also include one or more pads. The one or more pads may be electrically coupled to the one or more pins. In addition, the chip assembly may include a board that includes one or more board pads. Further, the chip assembly may include an anisotropic layer. The anisotropic layer may be positioned between the board and the one or more pads and between the board and a portion of the package substrate. In addition, the anisotropic layer may mechanically couple the board to the one or more pads and to the portion of the package substrate. Further, the anisotropic layer may electrically couple the one or more pads to the one or more board pads.

公开(公告)号：US11527481B2

公开(公告)日：2022-12-13

申请号：US17090933

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Choong Kooi Chee ,  Bok Eng Cheah ,  Teong Guan Yew ,  Jackson Chung Peng Kong ,  Loke Yip Foo

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/13 ,  H01L25/18 ,  H01L25/065

Abstract: According to various examples, a device is described. The device may include a package substrate. The device may also include a plurality of semiconductor devices disposed on the package substrate, wherein the plurality of semiconductor devices comprises top surfaces and bottom surfaces. The device may also include a plurality of interconnects coupled to the package substrate, wherein the plurality of interconnects are adjacent to the plurality of semiconductor devices. The device may also include a flyover bridge coupled to the top surfaces of the plurality of semiconductor devices and the plurality of interconnects, wherein the flyover bridge is directly coupled to the package substrate by the plurality of interconnects, and wherein the bottom surfaces of the plurality of semiconductor devices are electrically isolated from the package substrate.

公开(公告)号：US20210391238A1

公开(公告)日：2021-12-16

申请号：US17461459

申请日：2021-08-30

Applicant: Intel Corporation

Inventor： Loke Yip Foo ,  Choong Kooi Chee

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31 ,  H01L23/538 ,  H01L23/367 ,  H01L21/56

Abstract: Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.