Invention Grant
- Patent Title: Semiconductor processing system with in-situ electrical bias and methods thereof
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Application No.: US17662579Application Date: 2022-05-09
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Publication No.: US11837652B2Publication Date: 2023-12-05
- Inventor: David Hurley , Ioan Domsa , Ian Colgan , Gerhardus Van Der Linde , Patrick Hughes , Maciej Burel , Barry Clarke , Mihaela Ioana Popovici , Lars-Ake Ragnarsson
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: TOKYO ELECTRON LIMITED
- Current Assignee: TOKYO ELECTRON LIMITED
- Current Assignee Address: JP Tokyo
- Agency: Slater Matsil, LLP
- The original application number of the division: US16841342 2020.04.06
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/02 ; H01L21/67

Abstract:
A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.
Public/Granted literature
- US20220262921A1 Semiconductor Processing System with In-Situ Electrical Bias and Methods Thereof Public/Granted day:2022-08-18
Information query
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