公开(公告)号：US11335792B2

公开(公告)日：2022-05-17

申请号：US16841342

申请日：2020-04-06

Applicant: Tokyo Electron Limited

Inventor： David Hurley ,  Ioan Domsa ,  Ian Colgan ,  Gerhardus Van Der Linde ,  Patrick Hughes ,  Maciej Burel ,  Barry Clarke ,  Mihaela Ioana Popovici ,  Lars-Ake Ragnarsson

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/67

Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.

公开(公告)号：US11837652B2

公开(公告)日：2023-12-05

申请号：US17662579

申请日：2022-05-09

Applicant: Tokyo Electron Limited

Inventor： David Hurley ,  Ioan Domsa ,  Ian Colgan ,  Gerhardus Van Der Linde ,  Patrick Hughes ,  Maciej Burel ,  Barry Clarke ,  Mihaela Ioana Popovici ,  Lars-Ake Ragnarsson

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01L29/6684 ,  H01L21/02532 ,  H01L21/02554 ,  H01L21/02667 ,  H01L21/67098

Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.

公开(公告)号：US11894240B2

公开(公告)日：2024-02-06

申请号：US17185231

申请日：2021-02-25

Applicant: Tokyo Electron Limited

Inventor： David Hurley ,  Ioan Domsa ,  Ian Colgan ,  Gerhardus Van Der Linde ,  Patrick Hughes ,  Maciej Burel ,  Barry Clarke ,  Mihaela Ioana Popovici ,  Lars-Ake Ragnarsson ,  Gerrit J. Leusink ,  Robert Clark ,  Dina Triyoso

IPC: H01L21/326 ,  H01L21/04 ,  H01L21/42 ,  H01L21/02

CPC classification number: H01L21/326 ,  H01L21/02107 ,  H01L21/0425 ,  H01L21/42

Abstract: A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.

公开(公告)号：US20220262921A1

公开(公告)日：2022-08-18

申请号：US17662579

申请日：2022-05-09

Applicant: Tokyo Electron Limited

Inventor： David Hurley ,  Ioan Domsa ,  lan Colgan ,  Gerhardus Van Der Linde ,  Patrick Hughes ,  Maciej Burel ,  Barry Clarke ,  Mihaela Ioana Popovici ,  Lars-Ake Ragnarsson

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/67

Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.

公开(公告)号：US20210313444A1

公开(公告)日：2021-10-07

申请号：US16841342

申请日：2020-04-06

Applicant: Tokyo Electron Limited

Inventor： David Hurley ,  Ioan Domsa ,  Ian Colgan ,  Gerhardus Van Der Linde ,  Patrick Hughes ,  Maciej Burel ,  Barry Clarke ,  Mihaela Ioana Popovici ,  Lars-Ake Ragnarsson

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/67

Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.

公开(公告)号：US20210313189A1

公开(公告)日：2021-10-07

申请号：US17185231

申请日：2021-02-25

Applicant: Tokyo Electron Limited

Inventor： David Hurley ,  Ioan Domsa ,  Ian Colgan ,  Gerhardus Van Der Linde ,  Patrick Hughes ,  Maciej Burel ,  Barry Clarke ,  Mihaela Ioana Popovici ,  Lars-Ake Ragnarsson ,  Gerrit J. Leusink ,  Robert Clark ,  Dina Triyoso

IPC: H01L21/326 ,  H01L21/02 ,  H01L21/42 ,  H01L21/04

Abstract: A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.