- 专利标题: Lateral bipolar junction transistor including a stress layer and method
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申请号: US17555561申请日: 2021-12-20
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公开(公告)号: US11837653B2公开(公告)日: 2023-12-05
- 发明人: Jagar Singh , Alexander M. Derrickson , Alvin J. Joseph , Andreas Knorr , Judson R. Holt
- 申请人: GlobalFoundries U.S. Inc.
- 申请人地址: US NY Malta
- 专利权人: GlobalFoundries U.S. Inc.
- 当前专利权人: GlobalFoundries U.S. Inc.
- 当前专利权人地址: US NY Malta
- 代理机构: Hoffman Warnick LLC
- 代理商 Francois Pagette
- 主分类号: H01L29/73
- IPC分类号: H01L29/73 ; H01L29/737 ; H01L29/08 ; H01L29/66 ; H01L29/10
摘要:
Disclosed is a semiconductor structure with a lateral bipolar junction transistor (BJT). This semiconductor structure can be readily integrated into advanced silicon-on-insulator (SOI) technology platforms. Furthermore, to maintain or improve upon performance characteristics (e.g., cut-off frequency (fT)/maximum oscillation frequency (fmax) and beta cut-off frequency) that would otherwise be negatively impacted due to changing of the orientation of the BJT from vertical to lateral, the semiconductor structure can further include a dielectric stress layer (e.g., a tensilely strained layer in the case of an NPN-type transistor or a compressively strained layer in the case of a PNP-type transistor) partially covering the lateral BJT for charge carrier mobility enhancement and the lateral BJT can be configured as a lateral heterojunction bipolar transistor (HBT). Also disclosed is a method for forming the semiconductor structure.
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