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    INTEGRATED CIRCUIT STRUCTURE WITH THROUGH-METAL THROUGH-SUBSTRATE INTERCONNECT AND METHOD
    3.
    发明申请
    INTEGRATED CIRCUIT STRUCTURE WITH THROUGH-METAL THROUGH-SUBSTRATE INTERCONNECT AND METHOD 有权

    公开(公告)号：US20230034728A1

    公开(公告)日：2023-02-02

    申请号：US17389779

    申请日：2021-07-30

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Zhong-Xiang He ,  Richard J. Rassel ,  Alvin J. Joseph ,  Ramsey M. Hazbun ,  Jeonghyun Hwang ,  Mark D. Levy

    IPC: H01L21/768 ,  H01L23/48 ,  H01L29/778 ,  H01L29/66 ,  H01L21/8234

    Abstract: Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.

    SEMICONDUCTOR STRUCTURE WITH SEMICONDUCTOR-ON-INSULATOR REGION AND METHOD
    7.
    发明申请
    SEMICONDUCTOR STRUCTURE WITH SEMICONDUCTOR-ON-INSULATOR REGION AND METHOD 有权

    公开(公告)号：US20230125584A1

    公开(公告)日：2023-04-27

    申请号：US17934220

    申请日：2022-09-22

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Ramsey Hazbun ,  Alvin J. Joseph ,  Siva P. Adusumilli ,  Cameron Luce

    IPC: H01L21/02

    Abstract: Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.

    LATERAL BIPOLAR JUNCTION TRANSISTOR INCLUDING A STRESS LAYER AND METHOD
    8.
    发明申请
    LATERAL BIPOLAR JUNCTION TRANSISTOR INCLUDING A STRESS LAYER AND METHOD 有权

    公开(公告)号：US20230065785A1

    公开(公告)日：2023-03-02

    申请号：US17555561

    申请日：2021-12-20

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Jagar Singh ,  Alexander M. Derrickson ,  Alvin J. Joseph ,  Andreas Knorr ,  Judson R. Holt

    IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

    Abstract: Disclosed is a semiconductor structure with a lateral bipolar junction transistor (BJT). This semiconductor structure can be readily integrated into advanced silicon-on-insulator (SOI) technology platforms. Furthermore, to maintain or improve upon performance characteristics (e.g., cut-off frequency (fT)/maximum oscillation frequency (fmax) and beta cut-off frequency) that would otherwise be negatively impacted due to changing of the orientation of the BJT from vertical to lateral, the semiconductor structure can further include a dielectric stress layer (e.g., a tensilely strained layer in the case of an NPN-type transistor or a compressively strained layer in the case of a PNP-type transistor) partially covering the lateral BJT for charge carrier mobility enhancement and the lateral BJT can be configured as a lateral heterojunction bipolar transistor (HBT). Also disclosed is a method for forming the semiconductor structure.

    Semiconductor structure with semiconductor-on-insulator region and method
    9.
    发明授权
    Semiconductor structure with semiconductor-on-insulator region and method 有权

    公开(公告)号：US11515158B2

    公开(公告)日：2022-11-29

    申请号：US16815070

    申请日：2020-03-11

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Ramsey Hazbun ,  Alvin J. Joseph ,  Siva P. Adusumilli ,  Cameron Luce

    IPC: H01L21/02

    Abstract: Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.

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