Invention Grant
- Patent Title: Method of making an integrated circuit package including an integrated circuit die soldered to a bond pad of a redistribution structure
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Application No.: US17852766Application Date: 2022-06-29
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Publication No.: US11842955B2Publication Date: 2023-12-12
- Inventor: Chen-Hua Yu , Hung-Jui Kuo , Ming-Che Ho , Tzung-Hui Lee
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L21/48 ; H01L21/56 ; H01L21/683 ; H01L23/48 ; H01L23/485 ; H01L23/00 ; H01L23/31 ; H01L25/10

Abstract:
An integrated circuit package and a method of forming the same are provided. A method includes forming a first redistribution layer over a carrier, the first redistribution layer including a contact pad and a bond pad. A conductive pillar is formed over the contact pad. A backside surface of an integrated circuit die is attached to the bond pad using a solder joint. An encapsulant is formed along a sidewall of the conductive pillar and a sidewall of the integrated circuit die, a front-side surface of the integrated circuit die being substantially level with a topmost surface of the encapsulant and a topmost surface of the conductive pillar. A second redistribution layer is formed over the front-side surface of the integrated circuit die, the topmost surface of the encapsulant and the topmost surface of the conductive pillar.
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