公开(公告)号：US09899342B2

公开(公告)日：2018-02-20

申请号：US15164888

申请日：2016-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Hui Lee ,  Hung-Jui Kuo ,  Ming-Che Ho ,  Tzu-Yun Huang

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/11015 ,  H01L2224/12105 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2924/014

Abstract: A redistribution circuit structure electrically connected to at least one conductor underneath is provided. The redistribution circuit structure includes a dielectric layer, an alignment, and a redistribution conductive layer. The dielectric layer covers the conductor and includes at least one contact opening for exposing the conductor. The alignment mark is disposed on the dielectric layer. The alignment mark includes a base portion on the dielectric layer and a protruding portion on the base portion, wherein a ratio of a maximum thickness of the protruding portion to a thickness of the base portion is smaller than 25%. The redistribution conductive layer is disposed on the dielectric layer. The redistribution conductive layer includes a conductive via, and the conductive via is electrically connected to the conductor through the contact opening. A method of fabricating the redistribution circuit structure and an integrated fan-out package are also provided.

公开(公告)号：US11855014B2

公开(公告)日：2023-12-26

申请号：US17120825

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Ming-Che Ho ,  Hung-Jui Kuo ,  Yi-Wen Wu ,  Tzung-Hui Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/66 ,  H01L23/538

CPC classification number: H01L24/02 ,  H01L22/14 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/73 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/0215 ,  H01L2224/02125 ,  H01L2224/02185 ,  H01L2224/02315 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/11009 ,  H01L2224/1147 ,  H01L2224/11462 ,  H01L2224/13018 ,  H01L2224/13026 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/26125 ,  H01L2224/27009 ,  H01L2224/2747 ,  H01L2224/27462 ,  H01L2224/29018 ,  H01L2224/29036 ,  H01L2224/29147 ,  H01L2224/32227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/94 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73203 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/1147 ,  H01L2924/00014 ,  H01L2224/0215 ,  H01L2924/06 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/27

Abstract: A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

公开(公告)号：US11289373B2

公开(公告)日：2022-03-29

申请号：US16504328

申请日：2019-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yuan Teng ,  Bor-Rung Su ,  De-Yuan Lu ,  Hao-Yi Tsai ,  Tin-Hao Kuo ,  Tzung-Hui Lee ,  Tai-Min Chang

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/027 ,  H01L21/56

Abstract: A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.

公开(公告)号：US20210098397A1

公开(公告)日：2021-04-01

申请号：US17120825

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Ming-Che Ho ,  Hung-Jui Kuo ,  Yi-Wen Wu ,  Tzung-Hui Lee

IPC: H01L23/00 ,  H01L21/66

Abstract: A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

公开(公告)号：US20200043782A1

公开(公告)日：2020-02-06

申请号：US16504328

申请日：2019-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yuan Teng ,  Bor-Rung Su ,  De-Yuan Lu ,  Hao-Yi Tsai ,  Tin-Hao Kuo ,  Tzung-Hui Lee ,  Tai-Min Chang

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/027

Abstract: A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.

公开(公告)号：US10510646B2

公开(公告)日：2019-12-17

申请号：US15905756

申请日：2018-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Hui Lee ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: H01L23/498 ,  H01L25/11 ,  H01L23/31 ,  H01L21/48

Abstract: A package structure, a RDL structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a RDL structure, and a connector. The encapsulant is aside the die. The RDL structure is electrically connected to the die. The connector is connected to the die through the RDL structure. The RDL structure includes a dielectric layer, a first RDL and a second RDL. The dielectric layer is on the encapsulant and the die. The first RDL is penetrating through the dielectric layer to connect to the die, the first RDL comprises a first via and a first trace on the first via. The second RDL is on the first RDL. The second RDL comprises a second via and a second trace on the second via. The second via contacts and covers a portion of a top surface and a portion of sidewalls of the first trace.

公开(公告)号：US10461023B2

公开(公告)日：2019-10-29

申请号：US15884357

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Yen Chang ,  Hao-Yi Tsai ,  Kuo-Lung Pan ,  Tin-Hao Kuo ,  Tzung-Hui Lee ,  Teng-Yuan Lo ,  Hao-Chun Ting

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L25/10

Abstract: Semiconductor package s and methods of forming the same are disclosed. The semiconductor package includes a chip, a redistribution circuit structure and a UBM pattern. The redistribution circuit structure is disposed over and electrically connected to the chip and includes a topmost conductive pattern. The UBM pattern is disposed over and electrically connected to the topmost conductive pattern, wherein the UBM pattern includes a set of vias and a pad on the set of vias, wherein the vias are arranged in an array and electrically connected to the pad and the topmost conductive pattern.

公开(公告)号：US20190267314A1

公开(公告)日：2019-08-29

申请号：US15905756

申请日：2018-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Hui Lee ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L25/11

Abstract: A package structure, a RDL structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a RDL structure, and a connector. The encapsulant is aside the die. The RDL structure is electrically connected to the die. The connector is connected to the die through the RDL structure. The RDL structure includes a dielectric layer, a first RDL and a second RDL. The dielectric layer is on the encapsulant and the die. The first RDL is penetrating through the dielectric layer to connect to the die, the first RDL comprises a first via and a first trace on the first via. The second RDL is on the first RDL. The second RDL comprises a second via and a second trace on the second via. The second via contacts and covers a portion of a top surface and a portion of sidewalls of the first trace.

公开(公告)号：US10074623B2

公开(公告)日：2018-09-11

申请号：US15880568

申请日：2018-01-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Hui Lee ,  Hung-Jui Kuo ,  Ming-Che Ho ,  Tzu-Yun Huang

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/11015 ,  H01L2224/12105 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2924/014

Abstract: A redistribution circuit structure electrically connected to at least one conductor underneath is provided. The redistribution circuit structure includes a dielectric layer, an alignment, and a redistribution conductive layer. The dielectric layer covers the conductor and includes at least one contact opening for exposing the conductor. The alignment mark is disposed on the dielectric layer. The alignment mark includes a base portion on the dielectric layer and a protruding portion on the base portion, wherein a ratio of a maximum thickness of the protruding portion to a thickness of the base portion is smaller than 25%. The redistribution conductive layer is disposed on the dielectric layer. The redistribution conductive layer includes a conductive via, and the conductive via is electrically connected to the conductor through the contact opening. A method of fabricating the redistribution circuit structure and an integrated fan-out package are also provided.

公开(公告)号：US20170271283A1

公开(公告)日：2017-09-21

申请号：US15164888

申请日：2016-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Hui Lee ,  Hung-Jui Kuo ,  Ming-Che Ho ,  Tzu-Yun Huang

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/11015 ,  H01L2224/12105 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2924/014

Abstract: A redistribution circuit structure electrically connected to at least one conductor underneath is provided. The redistribution circuit structure includes a dielectric layer, an alignment, and a redistribution conductive layer. The dielectric layer covers the conductor and includes at least one contact opening for exposing the conductor. The alignment mark is disposed on the dielectric layer. The alignment mark includes a base portion on the dielectric layer and a protruding portion on the base portion, wherein a ratio of a maximum thickness of the protruding portion to a thickness of the base portion is smaller than 25%. The redistribution conductive layer is disposed on the dielectric layer. The redistribution conductive layer includes a conductive via, and the conductive via is electrically connected to the conductor through the contact opening. A method of fabricating the redistribution circuit structure and an integrated fan-out package are also provided.