公开(公告)号：US12288729B2

公开(公告)日：2025-04-29

申请号：US18435362

申请日：2024-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Sung Huang ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Hao-Yi Tsai ,  Chi-Ming Tsai ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Che Ho

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/16 ,  H01L23/522 ,  H01L23/528

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

公开(公告)号：US11855014B2

公开(公告)日：2023-12-26

申请号：US17120825

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Ming-Che Ho ,  Hung-Jui Kuo ,  Yi-Wen Wu ,  Tzung-Hui Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/66 ,  H01L23/538

CPC classification number: H01L24/02 ,  H01L22/14 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/73 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/0215 ,  H01L2224/02125 ,  H01L2224/02185 ,  H01L2224/02315 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/11009 ,  H01L2224/1147 ,  H01L2224/11462 ,  H01L2224/13018 ,  H01L2224/13026 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/26125 ,  H01L2224/27009 ,  H01L2224/2747 ,  H01L2224/27462 ,  H01L2224/29018 ,  H01L2224/29036 ,  H01L2224/29147 ,  H01L2224/32227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/94 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73203 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/1147 ,  H01L2924/00014 ,  H01L2224/0215 ,  H01L2924/06 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/27

Abstract: A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

公开(公告)号：US11626339B2

公开(公告)日：2023-04-11

申请号：US17201856

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Sung Huang ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Hao-Yi Tsai ,  Chi-Ming Tsai ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Che Ho

IPC: H01L23/31 ,  H01L23/16 ,  H01L23/522 ,  H01L21/768 ,  H01L21/56 ,  H01L23/528

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

公开(公告)号：US11024581B2

公开(公告)日：2021-06-01

申请号：US16283836

申请日：2019-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: H01L23/532 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768

Abstract: Semiconductor packages and methods of forming the same are disclosed. One of the semiconductor packages includes a first dielectric layer, a first conductive pattern and a barrier layer. The first conductive pattern is disposed in a second dielectric layer over the first dielectric layer. The barrier layer is disposed at an interface between the first conductive pattern and the second dielectric layer and an interface between the first dielectric layer and the second dielectric layer.

公开(公告)号：US10985116B2

公开(公告)日：2021-04-20

申请号：US16352838

申请日：2019-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wen Chen ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package and a method of forming the same are disclosed. A method of forming a semiconductor package includes the following operations. A polymer layer is formed over a die. A metal feature is formed in the polymer layer. An argon-containing plasma treatment is performed to the polymer layer and the metal feature.

公开(公告)号：US20210098397A1

公开(公告)日：2021-04-01

申请号：US17120825

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Ming-Che Ho ,  Hung-Jui Kuo ,  Yi-Wen Wu ,  Tzung-Hui Lee

IPC: H01L23/00 ,  H01L21/66

Abstract: A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

公开(公告)号：US10957645B1

公开(公告)日：2021-03-23

申请号：US16572609

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ming Lee ,  Chiang-Hao Lee ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: H01L23/48 ,  H01L21/4763 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528

Abstract: A package structure includes a semiconductor die and a redistribution circuit structure. The redistribution circuit structure is disposed on and electrically connected to the semiconductor die and includes a metallization layer and a dielectric layer disposed on the metallization layer. The metallization layer has conductive patterns, where each of the conductive patterns includes crystal grains, the crystal grains each are in a column shape and include a plurality of first banded structures having copper atoms oriented on a (220) lattice plane.

公开(公告)号：US10510646B2

公开(公告)日：2019-12-17

申请号：US15905756

申请日：2018-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Hui Lee ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: H01L23/498 ,  H01L25/11 ,  H01L23/31 ,  H01L21/48

Abstract: A package structure, a RDL structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a RDL structure, and a connector. The encapsulant is aside the die. The RDL structure is electrically connected to the die. The connector is connected to the die through the RDL structure. The RDL structure includes a dielectric layer, a first RDL and a second RDL. The dielectric layer is on the encapsulant and the die. The first RDL is penetrating through the dielectric layer to connect to the die, the first RDL comprises a first via and a first trace on the first via. The second RDL is on the first RDL. The second RDL comprises a second via and a second trace on the second via. The second via contacts and covers a portion of a top surface and a portion of sidewalls of the first trace.

公开(公告)号：US20190341322A1

公开(公告)日：2019-11-07

申请号：US16517679

申请日：2019-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Tseng ,  Hung-Jui Kuo ,  Ming-Che Ho ,  Chia-Hung Liu

IPC: H01L23/31 ,  H01L21/56 ,  H01L25/10 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L25/00 ,  H01L21/683

Abstract: A semiconductor package includes an encapsulated semiconductor device, a redistribution structure, and a protection layer. The encapsulated semiconductor device includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. The redistribution structure is disposed on the encapsulated semiconductor device and includes a dielectric layer and a redistribution circuit layer electrically connected to the semiconductor device. The protection layer at least covers the dielectric layer, wherein an oxygen permeability or a water vapor permeability of the protection layer is substantially lower than an oxygen permeability or a vapor permeability of the dielectric layer.

公开(公告)号：US20190279929A1

公开(公告)日：2019-09-12

申请号：US16416278

申请日：2019-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00 ,  H01L23/538

Abstract: An integrated fan-out package includes a die, an insulating encapsulation, a redistribution circuit structure, conductive terminals, and barrier layers. The insulating encapsulation encapsulates the die. The redistribution circuit structure includes a first redistribution conductive layer on the insulating encapsulation, a first inter-dielectric layer covering the first redistribution conductive layer, and a second redistribution conductive layer on the first inter-dielectric layer. The first redistribution conductive layer includes conductive through vias extending from a first surface of the insulating encapsulation to a second surface of the insulating encapsulation. The first inter-dielectric layer includes contact openings, portions of the second redistribution conductive layer filled in the contact openings are in contact with the first redistribution conductive layer and offset from the conductive through vias. The conductive terminals are disposed over the second surface of the insulating encapsulation. The barrier layers respectively are disposed between the conductive through vias and the conductive terminals.