- 专利标题: Low resistance crosspoint architecture
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申请号: US17468167申请日: 2021-09-07
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公开(公告)号: US11882774B2公开(公告)日: 2024-01-23
- 发明人: Rajasekhar Venigalla , Patrick M. Flynn , Josiah Jebaraj Johnley Muthuraj , Efe Sinan Ege , Kevin Lee Baker , Tao Nguyen , Davis Weymann
- 申请人: Micron Technology, Inc.
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 代理机构: Holland & Hart LLP
- 分案原申请号: US16684520 2019.11.14
- 主分类号: H10N70/00
- IPC分类号: H10N70/00 ; H01L21/768 ; H01L23/522 ; G11C13/00 ; H01L23/528 ; H10B63/00 ; H10N70/20
摘要:
Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.
公开/授权文献
- US20220069216A1 LOW RESISTANCE CROSSPOINT ARCHITECTURE 公开/授权日:2022-03-03
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