Invention Grant
- Patent Title: Selective margin testing to determine whether to signal train a memory system
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Application No.: US17421483Application Date: 2019-02-08
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Publication No.: US11894084B2Publication Date: 2024-02-06
- Inventor: Dujian Wu , Shijian Ge , Daocheng Bu
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jordan IP Law, LLC
- International Application: PCT/CN2019/074738 2019.02.08
- International Announcement: WO2020/160691A 2020.08.13
- Date entered country: 2021-07-08
- Main IPC: G11C29/10
- IPC: G11C29/10 ; G11C29/02 ; G11C29/38 ; G11C29/46 ; G11C29/12

Abstract:
Method, systems and apparatuses may provide for technology that executes a margin test of a first memory storage based on a subset of first signals associated with the first memory storage. The technology determines, based on the margin test, first margin data to indicate whether the first memory storage complies with one or more electrical constraints. The technology determines, based on the first margin data, whether to execute a signal training process.
Public/Granted literature
- US20220093197A1 SELECTIVE MARGIN TESTING TO DETERMINE WHETHER TO SIGNAL TRAIN A MEMORY SYSTEM Public/Granted day:2022-03-24
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