公开(公告)号：US11894084B2

公开(公告)日：2024-02-06

申请号：US17421483

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Dujian Wu ,  Shijian Ge ,  Daocheng Bu

IPC: G11C29/10 ,  G11C29/02 ,  G11C29/38 ,  G11C29/46 ,  G11C29/12

CPC classification number: G11C29/10 ,  G11C29/12005 ,  G11C29/12015 ,  G11C29/38 ,  G11C29/46

Abstract: Method, systems and apparatuses may provide for technology that executes a margin test of a first memory storage based on a subset of first signals associated with the first memory storage. The technology determines, based on the margin test, first margin data to indicate whether the first memory storage complies with one or more electrical constraints. The technology determines, based on the first margin data, whether to execute a signal training process.

公开(公告)号：US20210311818A1

公开(公告)日：2021-10-07

申请号：US17255109

申请日：2018-12-11

Applicant: INTEL CORPORATION

Inventor： Vincent Zimmer ,  Anil Agrawal ,  Dujian Wu ,  Shijian Ge ,  Zhenglong Wu

IPC: G06F11/07

Abstract: Systems, apparatuses and methods may provide for technology that handles failures in memory hardware (e.g., dynamic random access memory (DRAM)) via runtime post package repair. Such technology may include operations to perform a runtime post package repair in response to a memory hardware failure detected in the memory. In such an example, the runtime post package repair may be done after power up boot operations have been completed.