Invention Grant
- Patent Title: Flit-based parallel-forward error correction and parity
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Application No.: US17580408Application Date: 2022-01-20
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Publication No.: US11934261B2Publication Date: 2024-03-19
- Inventor: Debendra Das Sharma
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G06F11/07 ; G06F11/14 ; G06F13/42 ; H04L1/00 ; H04L1/1812

Abstract:
A flit-based packetization approach is used for transmitting information between electronic components. A protocol stack can generate transaction layer packets from information received from a transmitting device, assemble the transaction layer packets into one or more flits, and protect the flits with a flit-level cyclic redundancy check (CRC) scheme and a flit-level forward error correction or parallel-forward error correction (FEC) scheme. Flit-level FEC schemes can provide improved latencies and efficiencies over per-lane FEC schemes. To improve retry probability, flits can contain information indicating whether immediately preceding flits are null flits. Receivers can avoid sending a retry request for a corrupted flit if a seceding flit indicates the corrupted flit is a null fit. Parity flits can be used to protect groups of flits and correct single-flit errors.
Public/Granted literature
- US20220147417A1 FLIT-BASED PARALLEL-FORWARD ERROR CORRECTION AND PARITY Public/Granted day:2022-05-12
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