Invention Grant
- Patent Title: Electronic devices comprising reduced charge confinement regions in storage nodes of pillars and related methods
-
Application No.: US17092916Application Date: 2020-11-09
-
Publication No.: US11956954B2Publication Date: 2024-04-09
- Inventor: Yifen Liu , Yan Song , Albert Fayrushin , Naiming Liu , Yingda Dong , George Matamis
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: H10B43/27
- IPC: H10B43/27 ; H01L23/522 ; H10B43/10 ; H10B43/35 ; H10B43/40

Abstract:
An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.
Public/Granted literature
Information query