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    Memory device having memory cell strings and separate read and write control gates
    1.
    发明授权
    Memory device having memory cell strings and separate read and write control gates 有权

    公开(公告)号：US12200928B2

    公开(公告)日：2025-01-14

    申请号：US17387669

    申请日：2021-07-28

    Applicant: Micron Technology, Inc.

    Inventor： Haitao Liu ,  Kamal M. Karda ,  Albert Fayrushin ,  Yingda Dong

    IPC: H10B43/27 ,  H01L21/28 ,  H01L29/423 ,  H10B41/27

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell included in a memory cell string; the memory cell including charge storage structure and channel structure separated from the charge storage structure by a dielectric structure; a first control gate associated with the memory cell and located on a first side of the charge storage structure and a first side of the channel structure; and a second control gate associated with the memory cell and electrically separated from the first control gate, the second control gate located on a second side of the charge storage structure and a second side of the channel structure.

    SEQUENTIAL VOLTAGE RAMP-DOWN OF ACCESS LINES OF NON-VOLATILE MEMORY DEVICE
    3.
    发明申请
    SEQUENTIAL VOLTAGE RAMP-DOWN OF ACCESS LINES OF NON-VOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20220392533A1

    公开(公告)日：2022-12-08

    申请号：US17888041

    申请日：2022-08-15

    Applicant: Micron Technology, Inc.

    Inventor： Albert Fayrushin ,  Augusto Benvenuti ,  Akira Goda ,  Luca Laurin ,  Haitao Liu

    IPC: G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  G11C16/16 ,  G11C16/26

    Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.

    SEMICONDUCTOR DEVICES, ELECTRONIC SYSTEMS, AND RELATED METHODS
    4.
    发明申请
    SEMICONDUCTOR DEVICES, ELECTRONIC SYSTEMS, AND RELATED METHODS 审中-公开

    公开(公告)号：US20200083245A1

    公开(公告)日：2020-03-12

    申请号：US16123538

    申请日：2018-09-06

    Applicant: Micron Technology, Inc.

    Inventor： Albert Fayrushin ,  Haitao Liu ,  Mojtaba Asadirad

    IPC: H01L27/11582 ,  H01L29/10 ,  H01L23/522 ,  H01L23/528 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532

    Abstract: A semiconductor device comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, and a channel structure within an opening vertically extending through the stack and comprising a first semiconductor material having a first band gap. The semiconductor device also comprises a conductive plug structure within the opening and in direct contact with the channel region, and a band offset structure within the opening and in direct physical contact with the channel structure and the conductive plug structure. The band offset structure comprises a second semiconductor material having a second band gap different than the first band gap. The semiconductor device further comprises a conductive line structure electrically coupled to the conductive plug structure. A method of forming a semiconductor device and an electronic system are also described.

    MEMORY DEVICE HAVING MEMORY CELL STRINGS AND SHARED READ AND WRITE CONTROL GATES
    5.
    发明申请
    MEMORY DEVICE HAVING MEMORY CELL STRINGS AND SHARED READ AND WRITE CONTROL GATES 有权

    公开(公告)号：US20240389329A1

    公开(公告)日：2024-11-21

    申请号：US18666358

    申请日：2024-05-16

    Applicant: Micron Technology, Inc.

    Inventor： Albert Fayrushin ,  Haitao Liu ,  Kamal M. Karda

    IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

    Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory device, which includes a first memory cell string, a second memory cell string adjacent the first memory cell string, and a control gate. The first memory string includes a first channel structure, a first charge storage structure, and a first dielectric structure between the first channel structure and the first charge storage structure. The second memory cell string includes a second channel structure, a second charge storage structure, and a second dielectric structure between the second channel structure and the second charge storage structure. The control gate is separated from the first charge storage structure by a third dielectric structure and separated from the second channel structure by a fourth dielectric structure. The control gate and the first charge storage structure are between the first channel structure and the second channel structure.

    Sequential voltage ramp-down of access lines of non-volatile memory device
    8.
    发明授权
    Sequential voltage ramp-down of access lines of non-volatile memory device 有权

    公开(公告)号：US11417396B2

    公开(公告)日：2022-08-16

    申请号：US17067550

    申请日：2020-10-09

    Applicant: Micron Technology, Inc.

    Inventor： Albert Fayrushin ,  Augusto Benvenuti ,  Akira Goda ,  Luca Laurin ,  Haitao Liu

    IPC: G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  G11C16/16 ,  G11C16/26

    Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.

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