Invention Grant
- Patent Title: Network and edge acceleration tile (NEXT) architecture
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Application No.: US17134361Application Date: 2020-12-26
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Publication No.: US11983131B2Publication Date: 2024-05-14
- Inventor: Patrick G. Kutch , Andrey Chilikin , Niall D. McDonnell , Brian A. Keating , Naveen Lakkakula , Ilango S. Ganga , Venkidesh Krishna Iyer , Patrick Fleming , Lokpraveen Mosur
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G06F13/40
- IPC: G06F13/40 ; G06F3/06 ; G06F9/50 ; G06F12/0802 ; G06F13/42

Abstract:
Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.
Public/Granted literature
- US12026116B2 Network and edge acceleration tile (NEXT) architecture Public/Granted day:2024-07-02
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