公开(公告)号：US10048977B2

公开(公告)日：2018-08-14

申请号：US14978569

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Thomas E. Willis ,  Kapil Sood ,  Ilango S. Ganga ,  Scott P. Dubal ,  Pradeepsunder Ganesh ,  Jesse C. Brandeburg

IPC: G06F9/455 ,  H04L12/931

Abstract: Methods and Apparatus for Multi-Stage VM Virtual Network Function and Virtual Service Function Chain Acceleration for NFV and needs-based hardware acceleration. Compute platform hosting virtualized environments including virtual machines (VMs) running service applications performing network function virtualization (NFV) employ Field Programmable Gate Array (FPGA) to provide a hardware-based fast path for performing VM-to-VM and NFV-to-NFV transfers. The FPGAs, along with associated configuration data are also configured to support dynamic assignment and performance of hardware-acceleration to offload processing tasks from processors in virtualized environments, such as cloud data centers and the like.

公开(公告)号：US20160020870A1

公开(公告)日：2016-01-21

申请号：US14698102

申请日：2015-04-28

Applicant: Intel Corporation

Inventor： Ilango S. Ganga ,  Luke Chang ,  Andrey Belogolovy ,  Ovchinnikov Andrei

IPC: H04L1/00 ,  G06F11/10

CPC classification number: H04L1/0043 ,  G06F11/10 ,  H03M13/33 ,  H03M13/63 ,  H03M13/6312 ,  H04L1/0041 ,  H04L1/0042 ,  H04L1/0047 ,  H04L1/0057 ,  H04L1/0058 ,  H04L1/0072 ,  H04L7/041 ,  Y02D30/32

Abstract: Techniques to perform forward error correction for an electrical backplane are described.

Abstract translation: 描述了用于执行电背板的前向纠错的技术。

公开(公告)号：US20170104554A1

公开(公告)日：2017-04-13

申请号：US15360005

申请日：2016-11-23

Applicant: Intel Corporation

Inventor： Ilango S. Ganga ,  Luke Chang ,  Andrey Belogolovy ,  Andrei Ovchinnikov

IPC: H04L1/00 ,  H03M13/00 ,  G06F11/10

CPC classification number: H04L1/0043 ,  G06F11/10 ,  H03M13/33 ,  H03M13/63 ,  H03M13/6312 ,  H04L1/0041 ,  H04L1/0042 ,  H04L1/0047 ,  H04L1/0057 ,  H04L1/0058 ,  H04L1/0072 ,  H04L7/041 ,  Y02D30/32

Abstract: Techniques to perform forward error correction for an electrical backplane are described.

公开(公告)号：US20150135177A1

公开(公告)日：2015-05-14

申请号：US14319570

申请日：2014-06-30

Applicant: Intel Corporation

Inventor： Ilango S. Ganga

IPC: G06F9/455

CPC classification number: H04L45/745 ,  G06F9/45558 ,  G06F15/16 ,  G06F2009/45591 ,  G06F2009/45595 ,  H04L45/66

Abstract: A method and system may provide virtual port communications. A data frame, containing a destination identifier in a destination field and payload, may be modified by inserting a first virtual machine tag therein. The first virtual machine tag may include a first virtual port identifier for identifying a first logical interface of a first virtual machine on a virtual machine host.

Abstract translation: 方法和系统可以提供虚拟端口通信。 可以通过在其中插入第一虚拟机标签来修改在目的地字段和有效载荷中包含目的地标识符的数据帧。 第一虚拟机标签可以包括用于识别虚拟机主机上的第一虚拟机的第一逻辑接口的第一虚拟端口标识符。

公开(公告)号：US11983131B2

公开(公告)日：2024-05-14

申请号：US17134361

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Patrick G. Kutch ,  Andrey Chilikin ,  Niall D. McDonnell ,  Brian A. Keating ,  Naveen Lakkakula ,  Ilango S. Ganga ,  Venkidesh Krishna Iyer ,  Patrick Fleming ,  Lokpraveen Mosur

IPC: G06F13/40 ,  G06F3/06 ,  G06F9/50 ,  G06F12/0802 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0679 ,  G06F9/5083 ,  G06F12/0802 ,  G06F13/4221 ,  G06F2212/6042 ,  G06F2213/0026 ,  G06F2213/40

Abstract: Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.

公开(公告)号：US09992125B2

公开(公告)日：2018-06-05

申请号：US15237689

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： Alain Gravel ,  Robert G. Southworth ,  Jonathan A. Dama ,  Ilango S. Ganga ,  Matthew J. Webb

IPC: H04L12/825 ,  H04L25/49 ,  H04J3/06 ,  H04L12/931 ,  H04L1/00 ,  H04L7/033 ,  H04L25/14 ,  H04L12/413

CPC classification number: H04L47/25 ,  H04J3/0697 ,  H04L1/00 ,  H04L1/0002 ,  H04L1/0041 ,  H04L1/0045 ,  H04L7/033 ,  H04L7/0331 ,  H04L12/413 ,  H04L25/14 ,  H04L25/49 ,  H04L49/352

Abstract: Technologies for high-speed data transmission including a network port logic having a communication lane coupled to a physical medium dependent/physical medium attachment (PMD/PMA) sublayer, a physical coding sublayer (PCS), and a media access control (MAC) sublayer. The communication lane receives serial binary data at a line speed such as 25 gigabits per second. The PMD/PMA converts the serial binary data into parallel data, and the PCS decodes that parallel data using a line code also used for a slower line speed such as 10 gigabits per second. The network port logic may include four independent communication lanes, with each communication lane coupled to a dedicated PMD/PMA, PCS, and MAC. The network port logic may also include a multi-lane PCS and multi-lane MAC to receive and transmit data striped over the four communication lanes. Other embodiments are described and claimed.

公开(公告)号：US09912442B2

公开(公告)日：2018-03-06

申请号：US15360005

申请日：2016-11-23

Applicant: Intel Corporation

Inventor： Ilango S. Ganga ,  Luke Chang ,  Andrey Belogolovy ,  Andrei Ovchinnikov

IPC: G06F11/00 ,  H04L1/00 ,  G06F11/10 ,  H03M13/00

CPC classification number: H04L1/0043 ,  G06F11/10 ,  H03M13/33 ,  H03M13/63 ,  H03M13/6312 ,  H04L1/0041 ,  H04L1/0042 ,  H04L1/0047 ,  H04L1/0057 ,  H04L1/0058 ,  H04L1/0072 ,  H04L7/041 ,  Y02D30/32

Abstract: Data is received from a physical coding sublayer (PCS) of a physical layer, where the physical layer comprises a BASE-R physical layer. The data is used to generate a forward error correction (FEC) block comprising a shortened cyclic code comprising 32 rows of a particular number of bits, the particular number of bits comprise payload bits generated from output of the PCS and one or more bits of transcoding overhead, wherein the FEC block further comprises 32 parity bits at the end of the FEC block. The FEC block is scrambled using a pseudo-noise sequence. The FEC block is sent to a physical medium attachment (PMA) sublayer of the physical layer.

公开(公告)号：US11716285B2

公开(公告)日：2023-08-01

申请号：US15396505

申请日：2016-12-31

Applicant: INTEL CORPORATION

Inventor： Ilango S. Ganga

IPC: H04L45/745 ,  G06F9/455 ,  G06F15/16 ,  H04L45/00

CPC classification number: H04L45/745 ,  G06F9/45558 ,  G06F15/16 ,  H04L45/66 ,  G06F2009/45591 ,  G06F2009/45595

Abstract: A method and system may provide virtual port communications. A data frame, containing a destination identifier in a destination field and payload, may be modified by inserting a first virtual machine tag therein. The first virtual machine tag may include a first virtual port identifier for identifying a first logical interface of a first virtual machine on a virtual machine host

公开(公告)号：US20170147385A1

公开(公告)日：2017-05-25

申请号：US15396514

申请日：2016-12-31

Applicant: INTEL CORPORATION

Inventor： Ilango S. Ganga

IPC: G06F9/455

CPC classification number: H04L45/745 ,  G06F9/45558 ,  G06F15/16 ,  G06F2009/45591 ,  G06F2009/45595 ,  H04L45/66

Abstract: A method and system may provide virtual port communications. A data frame, containing a destination identifier in a destination field and payload, may be modified by inserting a first virtual machine tag therein. The first virtual machine tag may include a first virtual port identifier for identifying a first logical interface of a first virtual machine on a virtual machine host

公开(公告)号：US09258082B2

公开(公告)日：2016-02-09

申请号：US13882605

申请日：2013-03-13

Applicant: Intel Corporation

Inventor： Kent C. Lusted ,  Ilango S. Ganga

IPC: H03M13/00 ,  H04L1/00 ,  H04L29/06

CPC classification number: H04L1/004 ,  H04L1/0009 ,  H04L1/203 ,  H04L1/24 ,  H04L69/24 ,  H04L2001/0092

Abstract: Apparatus, systems, and methods for resolving a forward error correction (FEC) protocol include requesting, by a network node element during an auto-negotiation period between the node element and a link partner, to resolve at least one FEC mode during a data mode period, wherein auto-negotiation period occurs before the data mode period. At least one channel quality parameter of at least one channel of a communication link between the network node element and the link partner are determined by the network node element during the data mode period. The network node determines, during the data mode period, whether to enable or disable at least one FEC mode for use by the network node element based on, at least in part, the at least one channel quality parameter.

Abstract translation: 用于解决前向纠错（FEC）协议的装置，系统和方法包括在节点单元和链路伙伴之间的自动协商周期期间由网络节点单元请求在数据模式期间解析至少一个FEC模式 周期，其中自动协商周期发生在数据模式周期之前。 网络节点单元和链路伙伴之间的通信链路的至少一个信道的至少一个信道质量参数由数据模式周期期间的网络节点元素确定。 网络节点在数据模式周期期间，至少部分地基于至少一个信道质量参数来确定是否启用或禁用由网络节点元素使用的至少一个FEC模式。