Disclosed herein are non-planar transistor (e.g., nanoribbon) arrangements having asymmetric gate enclosures on at least one side. An example transistor arrangement includes a channel material shaped as a nanoribbon, and a gate stack wrapping around at least a portion of a first face of the nanoribbon, a sidewall, and a portion of a second face of the nanoribbon. Portions of the gate stack provided over the first and second faces of the nanoribbon extend in a direction parallel to the longitudinal axis of the nanoribbon for a certain distance that may be referred to as a “gate length.” A portion of the gate stack wrapping around the sidewall of the nanoribbon does not extend along the entire gate length, but, rather, extends over less than a half of the gate length, e.g., about one third of the gate length, thus making the gate enclosure on that sidewall asymmetric.