Invention Grant
- Patent Title: Stress relief in semiconductor wafers
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Application No.: US17405265Application Date: 2021-08-18
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Publication No.: US11990425B2Publication Date: 2024-05-21
- Inventor: Hojin Kim , Stephen Mancini , Soo Doo Chae
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L21/311 ; H01L21/66 ; H01L23/00

Abstract:
This disclosure describes a method for fabricating a plurality of semiconductor devices in a semiconductor wafer includes: bowing a semiconductor wafer including a substrate by covering the substrate with a strained layer; forming trenches at locations in scribe lines of the semiconductor wafer, the scribe lines identifying areas between adjacent dies on the semiconductor wafer; and reducing the bowing of the semiconductor wafer by filling the trenches with a stress-compensation material.
Public/Granted literature
- US20220102289A1 Stress Relief in Semiconductor Wafers Public/Granted day:2022-03-31
Information query
IPC分类: