公开(公告)号：US12193231B2

公开(公告)日：2025-01-07

申请号：US17472213

申请日：2021-09-10

Applicant: Tokyo Electron Limited

Inventor： Soo Doo Chae ,  Karthikeyan Pillai ,  Lior Huli ,  Na Young Bae ,  Hojin Kim

IPC: H10B43/27 ,  H10B43/10

Abstract: In certain embodiments, a method of fabricating a device includes forming, on a substrate, a layer stack of alternating layers of a first spin-on material and a second spin-on material. Each layer of the first spin-on material and the second spin-on material is formed by spin-on deposition. The method includes etching first openings through the layer stack and filling the first openings with a third material. The method includes etching second openings through the layer stack, removing the first spin-on material from the layer stack, and replacing the first spin-on material with a fourth material. The fourth material is a first metal-containing material.

公开(公告)号：US20220115399A1

公开(公告)日：2022-04-14

申请号：US17472213

申请日：2021-09-10

Applicant: Tokyo Electron Limited

Inventor： Soo Doo Chae ,  Karthikeyan Pillai ,  Lior Huli ,  Na Young Bae ,  Hojin Kim

IPC: H01L27/11582

Abstract: In certain embodiments, a method of fabricating a device includes forming, on a substrate, a layer stack of alternating layers of a first spin-on material and a second spin-on material. Each layer of the first spin-on material and the second spin-on material is formed by spin-on deposition. The method includes etching first openings through the layer stack and filling the first openings with a third material. The method includes etching second openings through the layer stack, removing the first spin-on material from the layer stack, and replacing the first spin-on material with a fourth material. The fourth material is a first metal-containing material.

公开(公告)号：US20180233407A1

公开(公告)日：2018-08-16

申请号：US15895736

申请日：2018-02-13

Applicant: Tokyo Electron Limited

Inventor： Kandabara N. Tapily ,  Sangcheol Han ,  Soo Doo Chae

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L21/76897 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02263 ,  H01L21/02304 ,  H01L21/02312 ,  H01L21/28562 ,  H01L21/3105 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53295

Abstract: A substrate processing method for forming a self-aligned contact using selective SiO2 deposition is described in various embodiments. The method includes providing a planarized substrate containing a dielectric layer surface and a metal-containing surface, coating the dielectric layer surface with a metal-containing catalyst layer, and exposing the planarized substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiO2 layer on the metal-containing catalyst layer on the dielectric layer surface. According to one embodiment, the method further includes depositing an etch stop layer on the SiO2 layer and on the metal-containing surfaces, depositing an interlayer dielectric layer on the planarized substrate, etching a recessed feature in the interlayer dielectric layer and stopping on the etch stop layer above the metal-containing surface, and filling the recessed feature with a metal.

公开(公告)号：US11915931B2

公开(公告)日：2024-02-27

申请号：US17406612

申请日：2021-08-19

Applicant: Tokyo Electron Limited

Inventor： Choong-man Lee ,  Soo Doo Chae ,  Angelique Raley ,  Qiaowei Lou ,  Toshio Hasegawa ,  Yoshihiro Kato

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/31144

Abstract: A method for fabricating a semiconductor device is described that includes forming a base layer over a top layer of a substrate, the base layer includes a silicon based dielectric having a thickness less than or equal to 5 nm and greater than or equal to 0.5 nm; forming a photoresist layer over the base layer, the photoresist including a first side and an opposite second side; exposing a first portion of the photoresist layer to a pattern of extreme ultraviolet (EUV) radiation from the first side; exposing a second portion of the photoresist layer with a pattern of electron flux from the second side, the electron flux being directed into the photoresist layer from the base layer in response to the EUV radiation; developing the exposed photoresist layer to form a patterned photoresist layer; and transferring the pattern of the patterned photoresist layer to the base layer and the top layer.

公开(公告)号：US20210288069A1

公开(公告)日：2021-09-16

申请号：US17197144

申请日：2021-03-10

Applicant: Tokyo Electron Limited

Inventor： Soo Doo Chae ,  Sang Cheol Han ,  Youngwoo Park

IPC: H01L27/11582

Abstract: In certain embodiments, a 3D structure for a microelectronic workpiece includes a multilayer stack that includes polysilicon layers separated by other layers, holes formed within the multilayer stack, recesses formed within the polysilicon layers at edges of the holes, conductive material deposited within the recesses to form outer layers within the holes, and plugs formed adjacent the outer layers within the holes.

公开(公告)号：US10978307B2

公开(公告)日：2021-04-13

申请号：US16938049

申请日：2020-07-24

Applicant: Tokyo Electron Limited

Inventor： David O'Meara ,  Eric Chih-Fang Liu ,  Richard Farrell ,  Soo Doo Chae

IPC: H01L21/3065 ,  H01L21/033 ,  H01L21/02

Abstract: A method of patterning a substrate includes receiving a substrate having microfabricated structures, including mandrels; executing a deposition process that deposits a first material on the mandrels, the deposition process including cyclically moving the substrate through a set of deposition modules. The substrate is moved through the set of deposition modules so that the first material is deposited at a first thickness at top portions of the mandrels and at a second thickness at bottom portions of mandrels, the first thickness being greater than the second thickness. The method includes executing a spacer deposition process that conformally deposits a second material on the substrate; executing a spacer open etch that removes depositions of the second material from over a top surface of the mandrels; removing the first material and the mandrels from the substrate, leaving sidewall spacers; and transferring a pattern defined by the sidewall spacers into an underlying layer.

公开(公告)号：US20210057226A1

公开(公告)日：2021-02-25

申请号：US16938049

申请日：2020-07-24

Applicant: Tokyo Electron Limited

Inventor： David O'Meara ,  Eric Chih-Fang Liu ,  Richard Farrell ,  Soo Doo Chae

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/033

Abstract: A method of patterning a substrate includes receiving a substrate having microfabricated structures, including mandrels; executing a deposition process that deposits a first material on the mandrels, the deposition process including cyclically moving the substrate through a set of deposition modules. The substrate is moved through the set of deposition modules so that the first material is deposited at a first thickness at top portions of the mandrels and at a second thickness at bottom portions of mandrels, the first thickness being greater than the second thickness. The method includes executing a spacer deposition process that conformally deposits a second material on the substrate; executing a spacer open etch that removes depositions of the second material from over a top surface of the mandrels; removing the first material and the mandrels from the substrate, leaving sidewall spacers; and transferring a pattern defined by the sidewall spacers into an underlying layer.

公开(公告)号：US10770294B2

公开(公告)日：2020-09-08

申请号：US16447565

申请日：2019-06-20

Applicant: Tokyo Electron Limited

Inventor： David O'Meara ,  Lior Huli ,  Soo Doo Chae ,  Wan Jae Park

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311

Abstract: Methods are disclosed that selectively deposit a protective material on the top regions of patterned photoresist layers, such patterned EUV photoresist layers, to provide a protective cap that reduces erosion damage during etch processes used for pattern transfer. Some deposition of the protective material on the sidewalls of the patterned photoresist layer is acceptable, and any deposition of the protective material on the underlying layer below the patterned photoresist layer is preferably thinner than the deposition at the top of the photoresist pattern. Further, the selective deposition of protective caps can be implemented, for example, through the application of high-rotation speeds to spatial atomic layer deposition (ALD) techniques. The selective deposition of protective caps increases the flexibility of options to improve etch resistance for various processes/materials.

公开(公告)号：US20240071984A1

公开(公告)日：2024-02-29

申请号：US17894105

申请日：2022-08-23

Applicant: Tokyo Electron Limited

Inventor： Kandabara Tapily ,  Soo Doo Chae ,  Satohiko Hoshino ,  Hojin Kim ,  Adam Gildea

IPC: H01L23/00 ,  C23C16/40 ,  C23C16/455 ,  C23C16/56

CPC classification number: H01L24/80 ,  C23C16/403 ,  C23C16/45536 ,  C23C16/56 ,  H01L2224/80011 ,  H01L2224/8002 ,  H01L2224/80236 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Devices and methods for forming semiconductor devices are disclosed. The semiconductor device can include a plurality of semiconductor wafers. The plurality of semiconductor wafers can have a dielectric bonding layer disposed thereupon. The dielectric bonding layers can be treated to increase a bonding energy with other semiconductor wafers. A wafer having a treatment applied to a bonding layer can be bonded to another wafer.

公开(公告)号：US20230133927A1

公开(公告)日：2023-05-04

申请号：US17668719

申请日：2022-02-10

Applicant: Tokyo Electron Limited

Inventor： Sang Cheol Han ,  Sunghil Lee ,  Iljung Park ,  Soo Doo Chae

IPC: H01L27/115 ,  H01L21/768

Abstract: A three-dimensional (3D) memory structure includes a memory array formed on a side of a substrate, a far-back-end-of-line (FBEOL) structure formed on the memory array, and a back-end-of-line (BEOL) structure formed on another side of the substrate opposite the side on which the memory array and the BEOL structure are formed. Methodologies to fabricate the 3D memory structure are also disclosed and include forming the memory array on the substrate, forming the FBEOL on the memory array, flipping the substrate, and forming the BEOL on the opposite side of the substrate. Alternative 3D memory structures and fabrication methodologies are also disclosed.