- 专利标题: Packaging substrate with low thermal resistance and low parasitic inductance
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申请号: US17445786申请日: 2021-08-24
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公开(公告)号: US12040592B2公开(公告)日: 2024-07-16
- 发明人: Wei Shi , Hao Huang , Siu Kwan Cheung , Huanlin Zhu , Lijun Zhu
- 申请人: Lumentum Operations LLC
- 申请人地址: US CA San Jose
- 专利权人: Lumentum Operations LLC
- 当前专利权人: Lumentum Operations LLC
- 当前专利权人地址: US CA San Jose
- 代理机构: Harrity & Harrity, LLP
- 主分类号: H01S5/024
- IPC分类号: H01S5/024 ; H01L23/373 ; H01L23/498 ; H01S5/02315 ; H01S5/183
摘要:
A substrate may include a thermally conductive metal core having a top side and a bottom side, a first dielectric coating on the top side of the metal core, a second dielectric coating on the bottom side of the metal core, a first metal circuit layer formed above the first dielectric coating, and a second metal circuit layer formed under the second dielectric coating. In some implementations, the first dielectric coating and the second dielectric coating have thicknesses below sixty micrometers and respective thermal resistances under fifteen degrees Celsius per watt. In some implementations, one or more electrical currents flowing vertically across a dielectric coating have a low parasitic inductance based on the thickness of the dielectric coating, and the metal core may dissipate heat flowing across the dielectric coating and into the metal core.
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