Invention Grant
- Patent Title: Array processor using programmable per-dimension size values and programmable per-dimension stride values for memory configuration
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Application No.: US17361250Application Date: 2021-06-28
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Publication No.: US12086597B2Publication Date: 2024-09-10
- Inventor: Matthew Brandon Gately , Eric Jonathan Deal , Mark Willard Johnson
- Applicant: Silicon Laboratories Inc.
- Applicant Address: US TX Austin
- Assignee: Silicon Laboratories Inc.
- Current Assignee: Silicon Laboratories Inc.
- Current Assignee Address: US TX Austin
- Agency: Zagorin Cave LLP
- Main IPC: G06F9/32
- IPC: G06F9/32 ; G06F9/345
Abstract:
An apparatus includes an array processor to process at least one array. The apparatus further includes a memory coupled to the array processor. The at least one array is stored in memory with programmable per-dimension size and stride values.
Public/Granted literature
- US20220414050A1 Apparatus for Memory Configuration for Array Processor and Associated Methods Public/Granted day:2022-12-29
Information query
